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F2833x - XINTF Address Bus

Lori Heustess
Guru* 93410 points 
Dear Champs,

The F2833x reference design (sprc541) shows the interface between the F2833x and an 


ASRAM (please refer to page 4 of the schematics or to the following figure):

As far as I understand, the address lines (XA0-XA16) should be connected to the 


correspondent lines (A0-A16) in the ASRAM, however they are connected as follows:



XA[0..8] <=> A [0..8]
XA[9..15] <=> A[11..17]
XA16 <=> A9
A10 is connected to ground.
Is this the way it should be?
  • 0
    TI__Guru* 93410 points 
    Jacob,

All that matters is that an address from the 2833x goes to an address on the SRAM – the order is not important.  
    If you ignore the SRAM pin name, all addresses within the range XA[0:16] are accounted for.  

It was connected this particular way on the eZdsp for compatibility with other memory devices. This is a 
    generic memory pin out that is compatible across multiple vendors and memory depths. (See the note that 
    it is 64kx16, 128kx16 or 256kx16 compatible with this pin out). 

Regards,
Lori
  • 0 in reply to Lori Heustess
    Prodigy 100 points

    would 256kx16 require the using XA17 address line as well which is not connected on the EZDSP dwg, 2^18 = 256k x 16 wide for 256k x 16 ??  I'm confused about the 256kx16 compatible pin out ?

    thanks

    brent