This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28335 access EQEP1I and EQEP2I

Other Parts Discussed in Thread: TMS320F28335

We are using the eQEP module in the TMS320F28335 to interface two incremental encoders.  These encoders have a once per revolution index pulse.  I know that the eQEP module can latch the encoder counts on an index pulse edge, but is there a way for the application code to get the status of the index pulse signals?  I've read sprug05a.pdf (TMS320x2833x, 2823x Enhanced Quadrature Encoder Pulse (eQEP) Module) cover-to-cover and can't see how to expose the status of EQEP1I and EQEP2I to the application code.  That is, there does not appear to be a register which contains a bit to indicate whether or not the encoder read head is sitting on the index pulse.

Have I missed something?  Is it possible?

Alternatively, EQEP1I and EQEP2I are the same pins as GPIO53 and GPIO26 respectively.  Even though these pins are configured for use with the eQEP module (see below), is it still possible to read GPIO53 and GPIO26?

Thanks,
Michael

 

EALLOW;
 
GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0;     // Enable pull-up on GPIO50 (EQEP1A)
GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0;     // Enable pull-up on GPIO51 (EQEP1B)
GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0;     // Enable pull-up on GPIO53 (EQEP1I)
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO50 (EQEP1A)
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO51 (EQEP1B)
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO53 (EQEP1I)
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1;    // Configure GPIO50 as EQEP1A
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1;    // Configure GPIO51 as EQEP1B
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1;    // Configure GPIO53 as EQEP1I
GpioCtrlRegs.GPBCTRL.bit.QUALPRD2 = kQUAL_SAMPLE_TIME;  // Qualification sampling time for GPIO48..55
 
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0;     // Enable pull-up on GPIO24 (EQEP2A)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0;     // Enable pull-up on GPIO25 (EQEP2B)
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0;     // Enable pull-up on GPIO26 (EQEP2I)  
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO24 (EQEP2A)
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO25 (EQEP2B)
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = kQUAL_SAMPLES;   // Sync to SYSCLKOUT GPIO26 (EQEP2I)
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2;    // Configure GPIO24 as EQEP2A
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2;    // Configure GPIO25 as EQEP2B
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2;    // Configure GPIO26 as EQEP2I
GpioCtrlRegs.GPACTRL.bit.QUALPRD3 = kQUAL_SAMPLE_TIME;  // Qualification sampling time for GPIO24..31
 
EDIS;