some FAE tell me that it can not compile the C2xLP instructions on CCS5.2 .but i try to compile C28x codes mixed with C2xLP codes, ti works. i don't know what is the problem.
the code is: (concerto)
.global _c_int00
.include "inc/sfr.asm"
.include "inc/constant.asm"
.include "inc/ram.asm"
*******************************************************************************
* VECTOR ADDRESS DECLARATIONS
*******************************************************************************
.SECT "RESET"
B _c_int00
.SECT "CSMZERO"
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7F80H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7F90H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7FA0H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7FB0H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7FC0H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7FD0H
.WORD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;3F7FE0H
.WORD 0,0,0,0,0,0 ;3F7FF5H
.SECT "PASSWORD"
.WORD 3104H ;0
.WORD 1388H ;1
.WORD 5410H ;2
.WORD 0AC80H ;3
.WORD 7513H ;4
.WORD 0705H ;5
.WORD 0F66CH ;6
.WORD 4422H ;7
.text
_c_int00:
main:
EALLOW ;
SETC OBJMODE;C28OBJ = 1 enable 28x object moDe
CLRC PAGE0 ;PAGE0 = 0 not relevant for 28x moDe,cleareD to zero
CLRC AMODE ;AMODE = 0 enable C28x addressing mode
SETC SXM ;SXM = 1 for C2xLP at reset, SXM = 0,for 28x at reset
SETC C ;Carry bit =1 for C2xLP at reset,Carry bit = 0 for 28x at reset
SPM 0 ;Set proDuct shift moDe zero, that is PM bits = 001 compatible to C2xLP PM reset;moDe
************************************
MOVL XAR6, #0x000041
MOVL XAR4, #0x009000
MOVL XAR5, #0x138000
MOVL ACC, @XAR6
MOVL P, ACC
MOV AL, @PL
MOVL XAR0, @XAR4
MOVL XAR7, @XAR4
SBF 7, EQ
ADDB AL, #-1
MOVZ AR6, @AL
MOV AL, *XAR5++
MOV *XAR7++, AL
BANZ -2,AR6--
MOV AL, @PL
MOVZ AR6, @AL
MOVL ACC, P
CMPL ACC, @XAR6
SBF 16, EQ
MOV AH, @PH
SBF 14, EQ
MOVL ACC, P
ADDB AH, #-1
MOVZ AR4, @AH
MOVL XAR6, #0x3ffffe
MOV AL, *XAR5++
MOV *XAR7++, AL
BANZ -2,AR6--
MOV AL, *XAR5++
MOV *XAR7++, AL
BANZ -8,AR4--
MOVL XAR4, @XAR0
************************************
.sect "ramfuncs"
;
MOVW DP,#FPAC1>>6
MOV FPAC1,#1 ;
MOV FBFALLBACK,#3 ;
MOVW DP,#FRD_INTF_CTRL>>6
MOV FRD_INTF_CTRL,#0
MOVW DP,#FRDCNTL>>6
MOV FRDCNTL,#300H
MOVW DP,#FRD_INTF_CTRL>>6
MOV FRD_INTF_CTRL,#3
MOVW DP,#ECC_ENABLE>>6
MOV ECC_ENABLE,#0AH ;
NOP;1
NOP;2
NOP;3
NOP;4
NOP;5
NOP;6
NOP;7
NOP;8
.text
MOVL XAR0,#0H
MOVL XAR1,#400H ;
MOVL XAR2,#0H
MOVL XAR3,#0H
MOVL XAR4,#0H
MOVL XAR5,#0H
MOVL XAR6,#0H
MOVL XAR7,#0H
MOVW DP,#PCLKCR0>>6
MOV PCLKCR0,#0000000000000101B
MOV PCLKCR1,#0100001011110000B
MOV HISPCP,#0 ;
MOV LOSPCP,#010B ;
MOVW DP,#GPACTRL>>6
MOV GPACTRL,#0 ;
MOV GPACTRL+1,#0
MOV GPAQSEL2,#1111111100000000B
MOV GPAQSEL2+1,#0000000000000000B ;
MOV GPAMUX2,#0101010100000000B
MOV GPAMUX2+1,#0000000000000000B
MOV ACC,#0
MOVL XAR7,#0H
MOV @AR0,#2000H
RAM_CLR_LOOP:
MOVL *XAR7++,ACC
BANZ RAM_CLR_LOOP,AR0--
MOVW DP,#TIMER2PRD>>6
MOV TIMER2PRD,#30000;
MOV TIMER2TCR,#1100000000100000B;
MOVW DP,#INT_T2>>6
MOVL XAR4,#T2_ISR
MOVL @0x1C,XAR4
MOVW DP,#PIECTRL>>6
MOV PIECTRL,#1 ;
AND IFR,#0FFFFH ;
OR IER,#0010000000000000B ;
CLRC INTM
*********************************************
*********************************************
MAINLOOP:
MOVW DP,#TIMER2_CNT>>6
TBIT TIMER2_CNT,#1
BF LOOP_COM,NTC
TCLR TIMER2_CNT,#1
MS1_LOOP:
**********************************************
**********************************************
LACL MS_CNT
ADD #1
SACL MS_CNT ;
LDP #MS_CNT>>7
BIT MS_CNT,BIT0
BCND MS2_LOOP_A,TC ;
B MS2_LOOP_B ;
MS2_LOOP_A:
**********************************************
**********************************************
LDP #MS_CNT>>7
BIT MS_CNT,BIT1
BCND MS4_LOOP_A,NTC
B MS4_LOOP_B
MS2_LOOP_B:
NOP
NOP
NOP
B LOOP_COM
**********************************************
**********************************************
MS4_LOOP_A:
NOP
NOP
NOP
B LOOP_COM
MS4_LOOP_B:
NOP
NOP
NOP
B LOOP_COM
LOOP_COM:
NOP
NOP
NOP
B MAINLOOP
***********************************************
***********************************************
T2_ISR:
LACL TIMER2_CNT
ADD #1
SACL TIMER2_CNT
IRET
.end