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Left justifies ADCRESULT registers

Isaac Pilli1
Intellectual 310 points

Hi,

Working with 320F28355, and reading ADC from its left justified registers.

From the ADC documentations:

" The ADCRESULTn registers are left justified when read from Peripheral Frame 2 (0x7108-0x7117) with two wait states "

What is the practical meaning of these wait states?

Does it mean that the ADCRESULT registers should be read into an external RAM with at least 2 wait states?

Or:

Does it mean that the results would be ready within the registers after some internal delay?

Or:

None of the above but something else?

Thanks,

Isaac

  • 0
    TI__Guru 60865 points

    0-wait state memory can be read in a single cycle.  2-wait state memory will require 2 additional cycles to read, for 3 cycles total.  The CPU pipeline will automatically stall to allow enough time for these reads to complete.  

    There is some explanation of this is the c28x core reference guide (http://www.ti.com/lit/ug/spru430e/spru430e.pdf) in section 4.3.1