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[Concerto] Fault when Reading CtoM RAM

Slava Ermachkov
Prodigy 210 points

Hi.

The M3 part goes to the Fault ISR when it tries to read a CTOM memory. The fault occurs when C28 subsystem is in Boot cycle or when C28 subsystem has executed a code that don't accessed the CTOM RAM. But, when C28's executed a code based on Dual IPC examples (with no IPC commands, but with write operations to CTOM on C28 side), the M3 subsystem reads a CTOM memory without a fault.

There are no any function calls (in main(), i don't know about startup code) that initializes C28's memory in both applications (that caused fault or not). In TRM was found only fetch protection and write protection bits for some RAM parts, but  what about "read protection"?

Why the M3 subsystem goes to the Fault ISR?

  • 0
    Prodigy 210 points

    Hi again.

    In addition to previous question.

    We expected that will be available the next algorithm (briefly). 1. The M3 starts and submits the IPC command "Boot to Flash" to C28. 2. If C28's flash is programmed, then C28's code places a signature into CTOM memory. 3. The M3's code polls the CTOM memory, and if a signature isn't detected at a time, loads a code into Shared memory and submits "Fetch".

    But, at 1st, the M3 subsystem goes to Fault ISR when it polls the CTOM memory (possible if the memory is not initialized, although the previous question wasn't answered). At 2nd, the F28M35H52's documentation contained a text: "This requires that the Master Flash be already programmed with valid code; otherwise, a hard fault exception is generated and the Cortex™-M3 goes back to the above reset sequence."

    Please explain, is it available to develop such a code for M3 subsystem that can detect, is a C28's flash programmed or not.