Hi,
I'm having an issue with the way I want to do my SPI communication. I think it's a timing issue but I just wanted to be sure and ask for help out here.
Basically, I'm doing a SPI communication between a F28335 ( MASTER ) and a F28035 ( SLAVE ).
Master Settings :
Clock Phase and Clock polarity = 0
Baud rate = 750kbit/s
RXFifo Interrupt enabled and Level = 1
TXFifo Interrupt enabled and Level = 4
Slave settings :
TXFifo interrupt disabled but TXFifo enabled
RXFifo interrupt enabled and Level = 1
Basically, the way it goes is like this. The master puts one word in TXBUF and then waits 50us. Slave will receive this word and put 4 words in its TXBUF. At the end of the 50us, MASTER will put 4 words in its TXBUF to clock out the 4 words stacked in the slave. In the MASTER RX interrupt, it will process each words received and process them.
What happens is that when the MASTER sends the 4 words to clock out the 4 words from the SLAVE, I get nothing correct. On the scope, I clearly see when the slave finishes to put its 4 words and it's way before the 50us ends. What I'm wondering is that, does the slave needs the spi clock from the master to put 4 words in its TX FIFO? If not, what else can be happening? At 750kbit/s, I was expecting it to be slow enough to work... My goal is to get this a lot faster...
Thanks!