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A question about proper use of TRANSFER SIZE when doing DMA transfers into shared memory buffer

Jeff Choate
Intellectual 610 points

Hello,

I have a basic question about the use of DMA that I couldn't really understand from the documentation.  I am hoping someone out there could give me a quick and easy answer to my question.

Let me start by explaining what I have.  It is pretty simple.  I have my DMA attached to a McBSP port in SPI mode which is collecting data from an external ADC (I am running on a 28346).  I have set up a buffer on my DSP which consists of 32 Uint16 words.  I want to read in 16 words of data and then signal my DSP to work with those 16 words that I read in.  IN the mean time, I want to continue reading 16 more words into the remaining 16 words of storage, at which time I want to signal the DSP again, and wrap the destination storage back to the start of the buffer.  

So basically, I have a 32 word circular buffer that I want to continuously fill with data, interrupting the DSP every 16 words read in.

I have this all configured and "running", but it is not really clean in the way I have done it.  I have my wrap configured for 32 bursts, (1 word per burst - SPI mode) with a step size of 1.  I then set the transfer size to 16, gave the interrupt, and made the channel run in continuous mode so that it would continue after the first 16 words.

What I saw happen is that it would read the first 16 words, interrupt the DSP, and then start writing the next 16 words back at the starting address.  After reading the documentation closer, I see that the transfer concludes the transaction, and that if run in continuous mode, it will reset the wrap counts and addresses when the transfer size is reset, restarting the transfer from scratch.  As you now know, this is not want I want!

So what I have done as a work around is to set the destination address for the DMA channel within the ISR that gets called from the transfer interrupt.  I manually reconfigure the destination address for the channel each time to force it to write to the location that I want it to go to.  This seems kludgey and wrong to me, but I cannot figure out a better way to accomplish what I am trying to do.

Is there a better way to accomplish what I am trying to do here?  Perhaps I shouldn't be using transfer size at all?

I am hoping this is an easy question for you experts out there - I appreciate any help or suggestions.

-Jeff

  • 0
    Intellectual 610 points

    I haven't heard anything on this question, so I will try simplifying the question to be more understandable!

    Assume you have a buffer of say, 6 words available to a DMA channel.

    Next that DMA channel will write data sequentially to that buffer starting at the first element and wrapping back to the 0th element after the end of the buffer is reached.

    To configure this DMA operation is trivial - set the wrap counter to 6, and set the mode to continuous so that it will continue to wrap.

    Now, assume that you want to issue an interrupt at the end of the 6th word so the DSP can consume the data.  Again, trivial - just set transfer size to 6, set the wrap counter to 0xFFFF, and set the channel interrupt to enable and it will do exactly what you want.

    OK - now the hard part that I need help with -  I want to interrupt after 3 words, and then continue to write the next 3 words and then interrupt after that, and then wrap to the beginning and go again.

    My problem is that I cannot see how to combine these different modes of operation.  If I want the interrupt, I need to use the transfer size.  My problem is that the transfer size is smaller than my wrap size.  Once the first transfer is over and the interrupt is issued, the wrap count is reinitialized when we run again, and the buffer goes back to the 0th element instead of continuing onto the 4th!

    Is there a way around this?  Like I said previously, I am kludging a workaround by re-programming the destination address manually each time the DSP runs the ISR.  This seems like a hack though and not very clean - it requires that the ISR knows all about the inner workings of the DMA engine which is not clean nor proper.

    Any suggestions on this?

    -Jeff