Hello everybody~~
I have some question about SCI FIFO register.
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SCI FIFO FFTX bits(4~0).These are compared with bits(12~8).When set bits(4~0) that exceed bits(12~8) ,then it will produce interrupt flag??........................(1)
SCI FIFO FFRX bits(4~0).These are compared with bits(12~8).When set bits(4~0) that exceed bits(12~8) ,then it will produce interrupt flag??.......................(2)
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SCI FIFO FFTX bits(5) set 1. it mean that when bits(4~0) small bits(12~8) or equal it,it will produce interrupt flag??.......................................................................(3)
These seems to be a contradiction between (1) and (3).
I want to know how those register to work?
Thank you
Best regards,
Tseng Adam