Hello,
I have enjoyed reading the AppNote SPRABS6 – October 2012 "Center-Aligned SVPWM Realization for 3- Phase 3- Level Inverter" written by Vieri Xue.
Anyway some questions came up while reading the appnote, for instance on page 10 :
"The positive pair of power switches is Qx1 and Qx3(x = R,S,T); the negative pair of the power
switches is Qx4 and Qx2(x = R,S,T)."
Can this be true ? - shouldn't it be :
"The positive pair of power switches is Qx1 and Qx2(x = R,S,T); the negative pair of the power
switches is Qx3 and Qx4(x = R,S,T)."
I haven't been able to get a reply to these questions by via "epic@ti.com" as Vieri Xue seemed to be unavailable at TI - despite the fact that the app note is quite fresh and that he should be still with TI.
I hope that in this forum there will be some people (hopefully from TI also ;) ) who have a common interest in implementing DSP- control like SVPWM not only for two-level inverters but also for the upcoming breed of multilevel inverters (starting with NPC) and that have also checked this quite fresh app note - maybe also Vieri Xue might be able to read this here and drop some highly appreciated remarks ...
The reason why this request is posted in the C2000 section is that I think the mentioned approach in this appnote should be lean enough to implement it also on a C2000-series MCU. Normaly FPGAs/CPLDs are common place in this arena ...
The appnote mentions that there was also done some kind of implementation and simulation for the approach. But as the sources are not available - even through "epic@ti.com" - it seems difficult to verify the approach as questions about the correct description in the app note remain. Therefore it would be quite helpful if someone at TI could "find" the simulation and implementation sources and contribute them for further evaluation to people like me that are interested in multilevel-inverter-control by DSP-MCUs like the C2000 series ...
If this shouldn't be the right section of the forum for my request please let me know and reallocate the post.
Lastly I would be glad to find some other forum members that are tackling similar issues with multilevel inverters and are willing to discuss possible SVPWM implementations for 3-level inverters in this thread ...
Hoping for some interest and "quick" replies, cheers
Thorsten
