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ADC Timing and PWM synchronisation

Paulin LEDESERT
Prodigy 75 points

Hello,

I am using a picollo 28035 for high speed regulation application, and i met some concern with adc timing.

My picollo is cadenced as 60Mhz

I am using two PWM as ADC trigger, one as 200kHz in up down mode, so TBPRD is 150 (I have no prescaler on PWM), and the second as 400kHz in up down mode, so TBPRD is 75. The two PWM are in phase.

I checked PWM timming with a oscilloscope, and it is good (I have unit test too on the configuration)

My 200kHz PWM is generating two interrupt with CMPA, the interrupt A with CMPA up and the second with CMPA down. CMPA is at 100 always. (I use this PWM only as ADC trigger)

My second PWM is generating an interrupt when counter reaches 0, once every two. I am using interrupt force register in way two have this interrupt the first and not the second time, so I have this interrupt, and then 100 tickst later my 200khz first interrupt, and 100 ticks later my third interrupt.

so my three PWM interrupt are on a range of 100 count. Each of this interrupt generate an adc trigger.

I dispose then my ADC conversion in three groups A, B and C.

In group A I have 6 conversion, and 5 in groups B and C.

My first interrupt of each group have a length of 7 tick  (there are used as "garbage" conversion, as specified in silicon errata), so ACQPS is 6

The other conversion have a length of 15 tick, so ACQPS is 14.

I checked ACQPS configuration with units tests. (as well as trigger configuration)

so for my group A adc conversion, I expeded that conversion time is 7 + (15 * 5) + 13 = 95 ticks, with 2 ticks as start conversion (as specified as Figure 34 of the Spurg5f), and 2 ticks for last result latch, total time for groupe A is 99).

As well, for my groupe B and C conversion, I need 7 + (15 * 5) + 13 + 4= 71 ticks.

So normally, each conversion group as finished when then  soc signal append for next group.

I enable an adc interrupt for one of EOC of group A interrupt, and the swith a led.

My problem is that when i check at the oscilloscope my led signal and my 200khz PWM, there are not synchronised. So i have a problem whith my adc timing configuration

When I change ACQPS for 13 (so 14 ticks of sample), I observe no problem, and my led signal is phasing with my pwm as expected.

When  ACQPS is at 14 and I disable one of the PWM interrupt, I observe no problem too.

I checked my configuration, ADCNONOVERLAP is at 0, whit unit test and debug mode, clock divider are at 0 too.

I don't understand where is my timing problem.

Can you confirm to me that my timing calculation is right?

Thank you

  • 0
    TI__Guru 57255 points

    Paulin,

    I think I understand your setup for the most part, however some things aren't quite clear to me:
    1) Are saying that you have 3 interrupt triggers per 200kHz?   Or have you setup 3 ADC:SOC triggers {each starting multiple SOCs} + 1 ADC:EOC interrupt?
    2) If there are 3 interrupt triggers, are the PWMs each generating an interrupt which then forces multiple ADC SOCs?  Or do the PWMs themselves generate the ADC SOCs?

    Your ADC timing calculations look to be valid, assuming everything is set up as you think.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Prodigy 75 points

    Hi Brett,

    Thank you for your answer.

    I use event trigger submodule of PWMs to setup 3 ADC:SOC triggers, starting multiple socs. I use also one EOC.

    Here is my code for the event trigger submodule

    //Epwm4Regs is 200khz, up down mode. CMPA is 100

        EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA;    
        EPwm4Regs.ETSEL.bit.SOCAEN = 1;              
        EPwm4Regs.ETPS.bit.SOCAPRD = 1;                
        EPwm4Regs.ETSEL.bit.SOCBSEL = ET_CTRD_CMPA;  
        EPwm4Regs.ETSEL.bit.SOCBEN = 1;                
        EPwm4Regs.ETPS.bit.SOCBPRD = 1;                

    //Epwm1 is 400kHz, in phase with Epwm4
        EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;    
        EPwm1Regs.ETSEL.bit.SOCAEN = 1;                
       EPwm1Regs.ETPS.bit.SOCAPRD = 2;     
          
        if(EPwm1Regs.ETPS.bit.SOCACNT == 0)
            EPwm1Regs.ETFRC.bit.SOCA = 1;          
        EPwm1Regs.ETCLR.bit.SOCA = 1;

    I can send you more code, but I prefers to use a private way for confidentiality.

    Cordially,

    Paulin

  • 0 in reply to Paulin LEDESERT
    Prodigy 75 points

    After some test, I have a question about the datasheet.

    In figure 34 in the ADC datasheet (Timing example for sequential mode /Eraly interrupt pulse), I see 6 ADCCLKs between the begining of a conversion and the beginning of the next sample. Is that time depends on the sample duration of the next sample?

    Because on the figure sample duration is 7, so 7 + 6 is 13 and there is no time betwen two conversion.

    Now if the sample duration is for example 10, have we a delay between two conversion? so do we have 6 ADCCLKs between the begining of a conversion and the beginning of the next sample or 3?

    Thank you

  • 0 in reply to Paulin LEDESERT
    TI__Guru 60865 points

    The pending sample will start 7 cycles before the end of the current conversion:

    Sample duration = 10:

    first 10 cycles: first sample, converter idle

    next 6 cycles: sample idle, first conversion

    next 7 cycles: second sample, first conversion (cont)

    next 3 cycles: second sample (cont), converter idle

    next 6 cycles: sample idle, second conversion

    ...

  • 0 in reply to Devin Cottier
    Prodigy 75 points

    Thank you for you answer, it is now clear to me.