Software Generation of GPIO pin interrupt

stevenh

Guru 20075 points

Hello,

I am writing unit tests for a module that requires a GPIO pin interrrupt (XINT1). Is it possible to software emulate the GPIO pin interrupt?

I tried the following:

1. Set PieVectTable.XINT1 = &TestIsr;

2. Set PieCtrlRegs.PIEIER1.bit.INTx8 = 1;

3. IER |= M_INT1;

3. Set IFR |= M_INT1;

4. Put a breakpoint in TestIsr

I am expecting the program to break at the TestIsr breakpont, however it always ends up in SEQ1INT_ISR. Why is this happening?

My program is not doing anything with the internal ADC.

After the program stopped in the SEQ1INT_ISR, PIEIER1 = 0x08 and not 0x01.

Why is this happening?

Stephen

over 13 years ago

0 stevenh over 13 years ago

Guru 20075 points

Ok, I got it to work. I just needed to set PieCtrlRegs.PIEIFR1.bit.INTx4 = 1.

It still seems quite strange to me that the SEQ1INT_ISR is occurring even though none of the PIEIFR1 bits are set.

Stephen

0 Lori Heustess over 13 years ago

TI__Guru* 93800 points

The CPU gets the ISR vector from the PIE for the specific group. The PIE will provide the vector in that group of the highest priority interrupt that is both (1) enabled in the PIEIERx.y and (2) flagged in the PIEIFRx.y. If there is no such interrupt both flagged and enabled, then the first interrupt in the group is fed to the CPU. So you need to be writing to the PIEIFR register instead of the CPU's IFR.

-Lori

0 Lori Heustess over 13 years ago in reply to Lori Heustess

TI__Guru* 93800 points

One caution - however - writing to the PIEIFR can be dangerous as you can disturb other flag bits resulting in missed interrupts.

0 stevenh over 13 years ago in reply to Lori Heustess

Guru 20075 points

Why would setting PieCtrlRegs.PIEIFR1.bit.INTx4 = 1 cause any of the other flag bits to be set?

Stephen

0 Lori Heustess over 13 years ago in reply to stevenh

TI__Guru* 93800 points

stevenh said:
Why would setting PieCtrlRegs.PIEIFR1.bit.INTx4 = 1 cause any of the other flag bits to be set?

This will result in a read of the register, modification, write back. If a bit is set between the read and the write it will be cleared by the operation and lost. If you endup with an interrupt vector request and no interrupt is flagged and enabled then you will get interrupt 1 which was not intended.

Regards

Lori

0 stevenh over 13 years ago in reply to Lori Heustess

Guru 20075 points

Thanks Lori.

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Software Generation of GPIO pin interrupt