problem with PWM external synchronization output signal SYNCO

Juan,

Since you aren't seeing any pulse at GPIO33, the issue is almost certainly on the PWM_sync_master.

You seem to be close from the C28x core side.  Have you had the master M3 code set GPIO33 to be owned by the C28x?


Thank you,
Brett

Yes I have. I run the example setup_m3 on the M3 side. As you well kown, that example gives C28x side the control of  all  GPIOs. I must say in addition that my scope is accurate enough (1GS/s) to display the 8-cycle-stretch SYNCO signal so I think I cannot see the pulse because it doesn't happen. 

Thank you very much Brett.

//Setup_m3.c

//Give C28 control of all GPIOs
GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
GPIOPinConfigureCoreSelect(GPIO_PORTJ_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);

Juan,

After looking again at the PWM settings, I believe that your PWM_sync_master is configured correctly.  In your PWM_sync_slave, I do see one definite issue:
EPwm1Params.TBCTL_PHSEN = 0;         ->        EPwm1Params.TBCTL_PHSEN = 1;
This should be done so that the slave synchronizes to the master's synch signal.  Note that there will likely be some more settings that you'll need to edit in order to make SYNCI work in the slave (since SYNCHI does not come in specifically at GPIO32).

I assume that EPwm1Params is set to be equal to EPwm1Regs, correct?

In order to capture the master's synch pulse (if it occurs), I would have your o-scope trigger a single acquisition at a rising-edge.  If a signal is never captured then you know the master is still configured wrong and there's where you should focus.  Once you know that the master is working you can then worry about the slave configuration.

Happy bug hunting!


Thank you,
Brett

Thanks for your answer Brett. As you say, the most important thing is to  find out why the SYNCI pulse isn't being sent to the GPIO33. This is my main concern right now.To my best knowledge, only three actions are needed to achieve that goal:

1. Give C28x the control of GPIO33:

• Done in example setup_m3

2. Set bit SYNCOSEL = 1  in the TBCTLRegister to enable periodic synco pulse:

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

3. Setup the GPIO 33 as SYNCO:

EALLOW;
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; 
EDIS;

Do I miss anything? I am really stuck with this issue and I am running out of ideas about what is happening.

Thank again, Brett.

Juan,

Without digging into this specifically, the 3 steps you've written down are my expectations as well.

A good experiment may be to, on the master, output a PWM from PWM2 that is equivalent to PWM1.  If PWM2 and PWM1 synch up you know that you've generated the synch pulse correctly (additionally you get some experience as to how PWM synchronization works on PWMs).  If you have other components tied to GPIO-33, another thought may be to see if you can output the SYNCO signal from GPIO-06.

In the mean time, I (or someone else at TI) will try to replicate the issue on our side in the next few days.  Let us know if you make progress on your side.


Thank you,
Brett

Hi Brett,

I have been working on the PWM synchronization for a few days and I have already carried out that experiment. I was able to synchronize the PWM1 and PWM2 easily. However I wasn't able to route the SYNC pulse to the GPIO33 or GPIO6 ( I tried both).Besides the two concerto cards, I also have a F28335 card. Using this card, I could output the SYNCO signal to GPIO33 without problems using practically the same code. It is really weird.

Hi again, I keep trying to output the SYNCO signal from GPIO33. I have modified the example epwm_deadband_c28 included in ControlSuite to enable the synco output feature.

The minimal modifications are as follows:

1. Call  the function InitEPwmSYncGpio()to setup the functionality of GPIO33

2. In function InitEpwm1Example() set the bit SYNCOSEL in TBCTL register to TB_CTR_ZERO (0x01);

As you see, the modifications are minimal. I run the example epwm_deadband_c28 on the C28x side and setup_m3 on the M3 side. Unfortunately, it doesn't work.

In the example epwm_deadband_c28,  the following comments appear in function InitEPwmSYncGpio():

/* Configure EPWMSYNC0 */
/* Enable internal pull-up for the selected pins */

// Pull-up enable should be set in the
// GPIO_O_PUR register in the M3 code.

Could the problem be in the M3 side? The example setup_m3  enables  the pull up resistor for all pins on GPIO_PORTA and GPIO_PORTB:

// Enable Pullups on EPWM(1-8)A/B capable pins
GPIOPadConfigSet(GPIO_PORTA_BASE, 0xFF, GPIO_PIN_TYPE_STD_WPU);
GPIOPadConfigSet(GPIO_PORTB_BASE, 0xFF, GPIO_PIN_TYPE_STD_WPU);

and I wonder if the setup of GPIO33 (which is located at GPIO port B) should be that way.

I attach the code modification for epwm_deadband_c28 below.

Regards,

// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F28M35x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwmSyncGpio();  // modification

void InitEPwm1Example()
{

EPwm1Regs.TBPRD = 6000; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // MODIFICATION. EPWM1SYNCO pulse

...

}

// Function in F28M3x5_EPwm.c

void InitEPwmSyncGpio(void)
{

EALLOW;

/* Configure EPWMSYNCI */

// EPWMSYNCI input is via the GPTRIPx mux's of the C28 GPIO Mux

/* Configure EPWMSYNC0 */
/* Enable internal pull-up for the selected pins */

// Pull-up enable should be set in the
// GPIO_O_PUR register in the M3 code.

// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Configures GPIO6 for EPWMSYNCO
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Configures GPIO33 for EPWMSYNCO

EDIS;

}

Hi, I have some news about the SYNCO pulse issue. I've tried to generate the SYNCO ouput pulse using the SWFSYNC signal. I used a modified version of the example epwm_deadband_c28. I just made a couple of change from the original project:

1.  At the end of function interrupt void epwm1_isr()

// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

EPwm1Regs.TBCTL.bit.SWFSYNC = 1; // MODIFICATION: it generates a SYNC0 pulse

2. In function  InitEPwm1Example():

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;  // MODIFICATION: EPW1SYNC0 = (SYNCI || SWFSYNC);

// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;  // MODIFICATION: Interrupt condtion CTR = PRD instead of CTR = Zero

3. In main(), I also call the function InitEPwmSyncGpio() to route the SYNCO signal as I described in the previous post.

// The prototype of this function is not included in F28M35x_GlobalPrototypes.h so we include here.

extern void InitEPwmSyncGpio(void);  // MODIFICATION

...

// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F28M35x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwmSyncGpio();  // MODIFICATION

Unfortunately, the SYNCO is still missing and no pulse can be seen from GPIO 33. I don't see what else I could do.

Best, Juan.

Juan,

I have reproduced your issue with the PWMSYNCHO pin output on GPIO33.

I am continuing to look into the issue internally and will respond back once we know more.


Thank you,
Brett

Great work, Brett! Thank you very much. It works perfectly now. I use a H52C1Development Kit and after populating the rows A and B of column #17 (GPIO33) in the the conectivity MUX with a jumper, everything started working fine. Now, the PWM modules are well synchronized. Thanks again, Brett. I don't think I would have found the issue on my own.

Regards, Juan.

Hi guys,

I'm having similar troubles with synchronizing the PWMs.

Til now I've only needed to sync the PWMs inside one card ( I'm using F28069). PWM1 is the master and it is synchronizing the next PWMs on CTR_ZRO. The next PWMs are set to give the SYNCO when SYNCI occurs. Everything works perfect.

Now, I need to sync the PWMs on two or more cards. I use GPIO33 as SYNCO and GPIO32 as SYNCI. The PWMs on the master card are ok (or seem ok, I've looked only at the first 4). The PWM1 from the slave card is programmed to be a slave PWM and to give the SYNCO on SYNCI. PWM1-slave is perfectly aligned with PWM1-master. But, the next PWMs are continuosly sliding to the right. If I disconnect the SYNCI from the slave card, the PWM1-slave starts sliding to the right as expected, but the next PWMs keep the same phase-shift with respect to PWM1-slave. This tells me that the PWMs inside the slave card are also synchronized, right?

Does anybody have an idea what am I doing wrong?

Thanks a lot,

Monica

Hi Monica,

I am not sure if you can conclude that the PWM outputs of the slave side are synchronized by disconnecting the two cards. In the slave side, the PWM1  module  expects to receive the SYNCI from GPIO32. I suppose you configured the PWM1 this way. I don't know how the PWM1 generates its SYNCO  from a SYNCI input if this signal cannot be found. I would suggest you to set the SYNCO of the PWM1 to CTR=0 or CTR=PRD in order to check that the sync between the PWM Modules on the slave side is correct.

Hi Juan,

I've tried that too, but the PWMs starting with no.2 are still sliding.

Now the only difference between the master and the slave cards is

EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; //slave

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //master

SYNCO is on CTR=0 in both cases.

I have no idea where I should look for the mistake.

And if I put on the scope SYNCO of both cards, they are identical. Then why the PWMs 2 to 8 are not aligned? I really don't get it....

Monica,

If you are following what Juan mentioned then the issue is undoubtedly with your slave-side (or less likely your slave device) and probably the configuration of PWM2-6 on the slave. 

Can you post the critical portion of your slave device's PWM configuration code?


Thank you,
Brett

Hi Brett,

Here is the PWM configuration. I've let everything I have in the code, maybe there's some setting that influences this and I didn't understand it right. The shadow registers are not 100% clear for me yet.

Thanks a lot,

Monica

EALLOW;
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;	// 0=GPIO,  1=I2C-SDA,  2=PWMSYNCI,  3=ADCSOCA
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 0;		// 1=OUTput,  0=INput
GpioCtrlRegs.GPBQSEL1.bit.GPIO32    = 2;   // qualification with 3 samples (=1), = 2 for 6 samples
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;	// 0=GPIO,  1=SCLA,  2=EPWMSYNCO,  3=ADCSOCB
GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1;		// 1=OUTput,  0=INput
EDIS;	
	
void init_epwm1(void)
{
   EALLOW;
   EPwm1Regs.TZSEL.bit.CBC5  = 1;
   EPwm1Regs.TZSEL.bit.CBC6  = 1;
   EPwm1Regs.TZSEL.bit.OSHT5 = 1;
   EPwm1Regs.TZSEL.bit.OSHT6 = 1;
   
   EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;    
   

   EPwm1Regs.TZEINT.bit.CBC = 1;
   EPwm1Regs.TZEINT.bit.OST = 1;
   EDIS;

   EPwm1Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm1Regs.TBCTR = 0x0000;          
   
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; 
   
   //Synchronization Output Select -slave card
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; 
   EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;  
   //Synchronization Output Select - master card
   /*
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
   */
   
   EPwm1Regs.TBPHS.half.TBPHS = 0x0000; 
   EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;
   
   
   EPwm1Regs.TBPRD 				= TRI_9KHz;         
   EPwm1Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm1Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;  
   
   
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;              
   EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;           
   EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;              
      
} 


void init_epwm2(void)
{
   
   EALLOW;
   EPwm2Regs.TZSEL.bit.CBC5  = 1;
   EPwm2Regs.TZSEL.bit.CBC6  = 1;
   EPwm2Regs.TZSEL.bit.OSHT5 = 1;
   EPwm2Regs.TZSEL.bit.OSHT6 = 1;

   EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;         
   
   EPwm2Regs.TZEINT.bit.CBC = 1;
   EPwm2Regs.TZEINT.bit.OST = 1;
   EDIS;
 
   EPwm2Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm2Regs.TBCTR = 0x0000;          

   EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm2Regs.TBPHS.half.TBPHS = 0x0000;             
   EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;       
   EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; 
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;    
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;      
   EPwm2Regs.TBPRD 				= TRI_9KHz;        
   EPwm2Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm2Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;  


   EPwm2Regs.CMPB               = 3760;
   EPwm2Regs.ETSEL.bit.SOCBEN	= 1;	            
   EPwm2Regs.ETSEL.bit.SOCBSEL	= ET_CTRD_CMPB;	    
   EPwm2Regs.ETPS.bit.SOCBPRD 	= ET_1ST;	        

   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;             
   EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;            
   EPwm2Regs.TBCTL.bit.FREE_SOFT = 3;             
} 


void init_epwm3(void)
{
   EALLOW;
   EPwm3Regs.TZSEL.bit.CBC5  = 1;
   EPwm3Regs.TZSEL.bit.CBC6  = 1;
   EPwm3Regs.TZSEL.bit.OSHT5 = 1;
   EPwm3Regs.TZSEL.bit.OSHT6 = 1;

   EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;            
   
   EPwm3Regs.TZEINT.bit.CBC = 1;
   EPwm3Regs.TZEINT.bit.OST = 1;
   EDIS;

   
   EPwm3Regs.TBCTL.bit.CTRMODE = 0x3;                
   EPwm3Regs.TBCTR = 0x0000;                        

   EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm3Regs.TBPHS.half.TBPHS = 0x0000;             
   EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; 
   EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;            
   EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      
   EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;         
   EPwm3Regs.TBPRD 				= TRI_9KHz;           
   EPwm3Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm3Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;	  

   EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;                
   EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;             
   EPwm3Regs.TBCTL.bit.FREE_SOFT = 3;                
} 


void init_epwm4(void)
{
  
   EALLOW;
   EPwm4Regs.TZSEL.bit.CBC5  = 1;
   EPwm4Regs.TZSEL.bit.CBC6  = 1;
   EPwm4Regs.TZSEL.bit.OSHT5 = 1;
   EPwm4Regs.TZSEL.bit.OSHT6 = 1;

   EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO;          
   
   EPwm4Regs.TZEINT.bit.CBC = 1;
   EPwm4Regs.TZEINT.bit.OST = 1;
   EDIS;

   EPwm4Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm4Regs.TBCTR = 0x0000;           

   EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm4Regs.TBPHS.half.TBPHS = 0x0000;                
   EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;
   EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;             
   EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      
   EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;         
   EPwm4Regs.TBPRD 				= TRI_9KHz;           
   EPwm4Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm4Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;	  

   EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;                
   EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;              
   EPwm4Regs.TBCTL.bit.FREE_SOFT = 3;                
} 


void init_epwm5(void)
{
   
   EALLOW;
   EPwm5Regs.TZSEL.bit.CBC5  = 1;
   EPwm5Regs.TZSEL.bit.CBC6  = 1;
   EPwm5Regs.TZSEL.bit.OSHT5 = 1;
   EPwm5Regs.TZSEL.bit.OSHT6 = 1;

   EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO;               

   EPwm5Regs.TZEINT.bit.CBC = 1;
   EPwm5Regs.TZEINT.bit.OST = 1;
   EDIS;

   EPwm5Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm5Regs.TBCTR = 0x0000;          
 
   EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm5Regs.TBPHS.half.TBPHS = 0x0000;                
   EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP;
   EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;
   EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      
   EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;         
   EPwm5Regs.TBPRD 				= TRI_9KHz;           
   EPwm5Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm5Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;	  


   EPwm5Regs.AQCTLA.bit.CAU = AQ_SET;                
   EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;                
   EPwm5Regs.TBCTL.bit.FREE_SOFT = 3;                
} 

void init_epwm6(void)
{
   
   EPwm6Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm6Regs.TBCTR = 0x0000;          
   
   EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm6Regs.TBPHS.half.TBPHS = 880;           
   EPwm6Regs.TBCTL.bit.PHSDIR = TB_DOWN;              
   
   EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;            
   EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      
   EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;         
   EPwm6Regs.TBPRD 				= TRI_9KHz;           
   EPwm6Regs.CMPA.half.CMPA     = TRI_CMPA; 

   EPwm6Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;	  

   EPwm6Regs.AQCTLA.bit.PRD = AQ_SET;               
   EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;                


   EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;              
   EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR;              
   EPwm6Regs.TBCTL.bit.FREE_SOFT = 3;               
} 


void init_epwm7(void)
{
  
   EALLOW;
   EPwm7Regs.TZSEL.bit.CBC5  = 1;
   EPwm7Regs.TZSEL.bit.CBC6  = 1;
   EPwm7Regs.TZSEL.bit.OSHT5 = 1;
   EPwm7Regs.TZSEL.bit.OSHT6 = 1;

   EPwm7Regs.TZCTL.bit.TZA = TZ_FORCE_LO;      
  
   EPwm7Regs.TZEINT.bit.CBC = 1;
   EPwm7Regs.TZEINT.bit.OST = 1;
   EDIS;

   EPwm7Regs.TBCTL.bit.CTRMODE = 0x3; 
   EPwm7Regs.TBCTR = 0x0000;          

   EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0; 

   EPwm7Regs.TBPHS.half.TBPHS = 0x0000;                
   EPwm7Regs.TBCTL.bit.PHSDIR = TB_UP;
   EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;            
   EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      
   EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;         
   EPwm7Regs.TBPRD 				= TRI_9KHz;          
   EPwm7Regs.CMPA.half.CMPA     = TRI_CMPA; 
   EPwm7Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UPDOWN;	  

   EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;              
   EPwm7Regs.AQCTLA.bit.CAD = AQ_CLEAR;             
   EPwm7Regs.TBCTL.bit.FREE_SOFT = 3;                
} 

I've read again about shadowing and if I got it right, shadowing is only doing good. The active registers will be updated on CTR=0, so actually when the SYNCI is received (in case of the PWMs with TBPHS=0). Please correct me if I didn't understand it right.

Thanks,

Monica

There's something else I've tested and doesn't look right.

I've changed the TBCTR of PWM2 to 0 while running. I was expecting to see the PWMs aligning after this 'error', but they remain out of phase. What is interesting is that the next PWMs in the chain (I've checked only 3 and 4) are aligned with PWM2. 

So I guess when I've seen the PWMs aligned in the master was just because I'm starting the PWM clocks at the same time.

I suggest you synchronize the two cards separately as starting point. If you make sure that your configuration works in each card, it will help you to find out what is wrong with the external sync.

Regards,

Thanks!

I've found the mistake. Sme time ago I've read that it's a good practice to refresh the registers if you still have some free CPU time. In the function I was calling between the interrupts I forgot to change the settings for PWM2 which was before used as master. In the previous version only PWM2, 3, 4, and 6 had to be synchronized, but now that I have to synchronize more cards, I have to use PWM1 as master and PWM2 is changed to slave mode.

The PWMs on both cards are synchronized now even after forcing a 0 in the counter register or changing the counting mode for a while.

I'll probably come back for tipps on sending the SYNCO between cards, as the environment where the cards have to work is pretty harsh.

All the best,

Monica