Hello,
I'm using the I2C interrupt (no FIFO) on the xF28027 Piccolo. I have interrupts enabled for XRDY, RRDY, and NACK, however it looks like I'm only getting into the ISR when there's a NACK.
I have a state machine that kicks off the transmission to read data from a slave. It configures the xF28027 as the master, sets the slave address, address to read from, Tx mode, etc as follows:
I2caRegs.I2CSAR = nAddress;
I2caRegs.I2CCNT = 1;
I2caRegs.I2CDXR = nCommand;
I2caRegs.I2CMDR.bit.TRX = 1;
I2caRegs.I2CMDR.bit.MST = 1;
I2caRegs.I2CMDR.bit.FREE = 1;
I2caRegs.I2CMDR.bit.STP = 0;
I2caRegs.I2CMDR.bit.STT = 1;
When I watch the data stream using an analyzer, I see that this first message gets ACK'd (slave address and data address), but then my ISR doesn't get triggered (I was expecting XRDY to be set here). As a result, the restart is never sent to read the actual data from the slave. Several milliseconds later, when it tries again, the slave ACKs its address, and then NACKs when I try to resend the data address. The ISR does trigger here, and the NACK conditional sends the stop bit... Then the process repeats.
I noticed that the XRDY status register flag appears set when the ISR gets entered for the NACK. I don't see why the interrupt doesn't get triggered after successfully sending the slave address, write bit, data address.
Thoughts?
