Hi,
I was taking a look at the shared memory and to the RAM_Management example.
About the SxRAM, the M3 can be the master (Write and Read) and so the C28 could only read. Or M3 could give access to C28 for a SxRAM which will become the master and M3 could only Read. Did I understand well?
Is there a way to have both core Writing and Reading in a Shared RAM section?
Thank you for your helping,
Marc
