F28335 MCBSP as SPI inetfacing with AD1258

I m interfacing ADS1258 with f28335 via MCBSP.

code for interfacing is:

for(;;)
{
mcbsp_xmit(sdata1,sdata2);
while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {} // Master waits until RX data is ready
rdata2 = McbspaRegs.DRR2.all; // Read DRR2 first.
rdata1 = McbspaRegs.DRR1.all; // Then read DRR1 to complete receiving of data
 delay_loop();
  asm(" nop"); // Good place for a breakpoint

}

code for configuration setting:

void init_mcbsp_spi()
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
 McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word

McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspaRegs.SRGR1.all= 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16

McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}

Clock is fine.

CS is fine.

Data output is fine.

While AS1258 doesn't give stable data. I m reading the default register values but it returns some random values.

START pin on ADC is 1, PDWN=1, RESET=1,

DRDY signal is also a bit unstable. It goes low n high but its width varies.

I tried with single byte read, but same type of Output observed. I changed SCLK ferquency but no effect.

I also tried sending data on falling edge n receiving data on rising edge of SCLK without luck.

for 8-bit transmission, code is: 

for(;;)
{
  McbspaRegs.DXR1.all=0x0045;     // register read, reg. ID=5
while( McbspaRegs.SPCR1.bit.RRDY == 0 ) {} // Master waits until RX data is ready
  rdata1 = McbspaRegs.DRR1.all; // Then read DRR1 to complete receiving of data
 delay_loop();
  asm(" nop"); // Good place for a breakpoint

}

 XCOMPAND n RCOMPAND adjusted. RWRDLEN=0  &  XWRDLEN =0

Help me PLZZZZZZZZZZZZ.

I dont understand where is the problem??????????????????