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Sequential ADC sampling probelms with pwm phase control.

Pavel Ruban
Intellectual 275 points


Hello, I have an issue with sequential ADC sampling;

C2000 DSP: F28035.

First of all here is the setup for my ADC acquisition:

ADCINT 1 is configured with SOC1, SOC2 and SOC3, which is triggered by PWM1 (Master) at a continuous 25kHZ rate.

ADCINT 3 is configured with SOC4, SOC5 and SOC6, which is triggered by PWM3 (Slave) at a continuous 25kHZ rate. PWM3 has a 120 degrees phase compared to PWM1.

ADCINT5 is configured with SOC7, SOC8and SOC9, which triggered by PWM5 (Slave) at a continuous 25kHZ rate. PWM3 has a 240 degrees phase compared to PWM1.

The sampling process is started by a CMPB event at a 1500 clock cycle (2400 cycles = 25 kHZ with 60Mhz processor).

I use an acquisition window of ACQPS = 6 for all the channels.

Everything works fine with this setup, and I first get problems when I add another channel for sampling:

ADCINT7 is configured with SOC10, which is triggered by PWM7 (Slave) at a continuous 300 kHZ rate. ACQPS=6. Period=199 (you can read topic: http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/247130.aspx

PWM7 is phase enabled so that the ADC sampling will not overlap with ADCINT1, 3 and 5.

Also I use early interrupt pulse for ADC configuration:

AdcRegs.ADCCTL1.bit.INTPULSEPOS = 0;

Theoretically I should not have any problems with ADC overlap if this is true:

The conversion and sampling process for ADCINT1, 3 and 5 takes 46 cycles. (refer to Figure. 34 p.40 SPRUGE5D).

The conversion and sampling for ADCINT7 is 7 ADCCLKs sampling + 13 ADC Clocks conversion. (20 in total).

So the ADCINT7 is more frequent than the other ADC interrupts, at a rate of 300kHz, and with phase enable it should be possible to have sequential sampling without any overlap, because the total sampling time will be 46 cycles + 20 cycles, where there will be 8 ADCINT7 interrupts in a cycle of 1 ADCINT1 interrupt.

There is unfortunately an issue, where I can see that 25kHz is been modulated in my 300kHz control algorithm. Im not sure if it is an issue with ADC sample/conversion overlapping or an ADC interrupt overlapping which introduces these problems. It seems that the sampling interval period is not constant, due to interference.

I have tested ADCINT1, 3, 5 alone and ADCINT7 alone, where everything works fine, but problems occur when I combine ADCINT1,3,5 and ADCINT7 together.

I have attached my ADC settings file.

Hope there is something I have overseen in the design, all help appreciated.

 7888.ADC.h

Best Regards,

Pavel.

  • 0
    Intellectual 275 points

    I would like to add that the 25kHz modulation into the 300kHz control loop comes from EPWM7 been phase enabled with respect to EPWM1 that runs 25kHz.

    The problem is, that I can't see another way of doing sequential sampling without overlapping, without having EPWM7 phase enabled.

  • 0 in reply to Pavel Ruban
    TI__Guru 60865 points

    Are you using 2399 or 2400 for the TBPRD value for EPWMs 1-6?

  • 0 in reply to Devin Cottier
    Intellectual 275 points

    Im using TBPRD = 2400 for EPWM1-6

    and TBPRD = 199 for EPWM7

  • 0 in reply to Pavel Ruban
    TI__Guru 60865 points

    If I am not mistaken, if you used TBPRD = 199 to get exactly 300KHz wouldn't you need to use TBPRD = 2399 to get exactly 25KHz?  I believe in the other post you said that all of the ePWMs are in up-count mode, not just ePWM7?  

  • 0 in reply to Devin Cottier
    Intellectual 275 points

    Yes thats true, all PWM channels run in up-count mode, and I need to use a TBPRD = 2399 to get an exact 25 kHz.

    Nevertheless there isn't much difference if I use a TBPRD of 2400 or 2399. Like I posted before the first problem is that having my 300kHz PWM been synchronised by a 25kHz PWM channel introduces a disturbance to the control loop. Then more disturbance comes when i need to do sequential sampling with all channels. It seems that my sampling trigger does not have a constant sampling interval. At least I can measure a deviation from when i enter my ADCINT interrupt by toggling a GPIO pin.

     

     

       

  • 0 in reply to Pavel Ruban
    Intellectual 275 points

    I have just tried measuring my pwm frequency with a TBPRD of 2399 to be 25.11 kHz with a period of around 39.82us. Thats a deviation of around 11 cycles.

    Any explanation for this? I get a precise 25kHz with 2410 TBPRD,

  • 0 in reply to Pavel Ruban
    TI__Guru 57255 points

    Pavel,

    One thought:
    Are you aware of the "ADC: Initial Conversion Errata" on the Piccolo ADC? 
    http://www.ti.com/lit/sprz295

    It may be a good idea to configure two ADC channels to be triggered by your PWM7 SOC and then use the second sample as the valid sample.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    TI__Guru 57255 points

    Pavel,

    The reason that 2410 gives you exactly 25kHz is likely because the precision of the system clock is not exactly 60MHz (by default the clock source is the internal oscillator).


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 275 points

    Hello Brett,

    Thank you for your reply. I was not aware of the Silicon errata for F28035, but now i can see that Initial Conversion Errata is causing some problems. (Also I had a dummy measurement for PWM1, inherited from the TI ADC.h file.)

    I have applied a dummy measurement for PWM7 and this has solved the problem for my PWM7 sampling, but the problem appeared instead on my PWM1!

    So now I'am wandering what to do to have the sampling working for all the channels. Perhaps the problem is caused, because of my always changing sequential sampling pattern?

    I start with (SOC0)-> SOC1 -> SOC2-> SOC3-> SOC10 ->SOC11 -> SOC10 ->SOC11 ->SOC10 ->SOC11->SOC10 ->SOC11 (SOC10 is my dummy sample for PWM7)

    then after 13.33us :

                     SOC4 -> SOC5-> SOC6-> SOC10 ->SOC11 -> SOC10 ->SOC11 ->SOC10 ->SOC11->SOC10 ->SOC11

    and after 26.66 us:

                     SOC7 -> SOC8-> SOC9-> SOC10 ->SOC11 -> SOC10 ->SOC11 ->SOC10 ->SOC11->SOC10 ->SOC11

     

    I have noticed that there isnt any problem for SOC4,5,6 that is triggered by PWM3 and also no problem for SOC7,8,9 but now I have sampling errors for my PWM1, when I add a PWM7 dummy sampling.

    A dummy sampling SOC0 for PWM1, doesn't seem to help.

     

    Any suggestions?

     

    Thank you in advance,

    Pavel

     

  • 0 in reply to Pavel Ruban
    TI__Guru 57255 points

    Pavel,

    What do you mean by 'the error appears on PWM1'?  (are all conversions triggered by PWM1 wrong, or just SOC0, or just SOC0&SOC1, etc?)

    Ideally SOC0 may fluctuate and be incorrect, but SOC1-SOC3 should be fine.  This assumes that SOC0-3 trigger off of the exact same PWM1 event (which I've assumed to this point). 

    The SOC sequences for PWM3 and 5 should ideally also have a dummy sample preceding them.

    The method of sampling SOC10+11 more frequently than the others ('changing the sequence') should not affect the results as long as the errata is followed.  I've done this type of thing several times successfully.  The key is often understanding the timing and knowing about the erratum.

    Hopefully this helps. :)


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 275 points

    Hello Brett,

     

    The Silicon errata for the adc is the answer to all the problems! I have a dummy measurment for each PWM channel and everything works perfect!

    The problem with PWM1 was another bug, which is irrelevant to this topic.

    Thank you very much, I appreciate the help!

     

    Regards,

    Pavel