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F28M36P63C2 Memory speed question

Marc Zetek
Intellectual 800 points

Hi,

On the block diagram of the Concerto chip, we can see a number of memories.

On the M3 side, we see memories designated as C0, C1, C2-C8 and C9-C15
On the C28 side, we see memories designated as L0, L1, L2, L3, M0 and M1
And finally, we see MtoC and CtoM shared memory, and some non-dedicated shared memories as well.

My question is -- are all of these memories single-cycle or are some memories faster than others?

A corollary question is -- when would we prefer ECC memory over parity memory?

Thank you,
Marc 

  • 0
    TI__Guru** 116581 points

    Hi Mark,

    Some of the RAMs are dedicated RAMs for CPU (C0/C1 for M3 and M0/M1/L0/L1 for C28x) and others are shared between CPU and their respective DMA. RAMs which are dedicated to CPU are single-cycle access RAMs. For other RAMs, if CPU and DMA both are accessing same shared memory same time then there will be an arbitration which  will casue extra cycles else these will also act like single-cycle access RAMs. Same will be the case with MtoC and CtoM shared RAMs.

    ECC memories have one bit correction logic where as in case of Parity memory, one bit error is uncorrectable. Also in case of Parity memory, two bit error can't be detected where as in case of ECC memory two bit error is detectable. Since device has limited ECC RAMs, one should use ECC memory for critical code only e.g. fault handlers.

    Regards,

    Vivek Singh