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Is there a second SCI on the F28M36x part C28 core?

I am getting ready to use the SCI ports on the C28 section of my M36 and found descriptions of registers for two SCIs, A and B in the Technical Reference Manual.  There is a note saying that B is not available on all chips.  The main function diagram in the datasheet shows 1 SCI. But in the datasheet for the M36 parts on page 74, C28X Peripheral Mode 1 there are two pins for the SCIRXDA and two for the SCITXDA as follows:

SCIRXDA    PE4_GPIO28     PF4_GPIO36

SCITXDA    PE5_GPIO29     PF3_GPIO35

Does this mean there are two outputs and two inputs for the peripheral in the same mode?  Or is this a typo and there are two ports available?  Finally, if I am using C28 mode 1 which is the correct pin set to connect my level shifters to?

  • Mike,

    There is only one SCI peripheral on the C28x side of the 'M36x device, SCI-A.  However, there are several potential ways to allow this one SCI peripheral to be muxed so that it reaches the outside world.  For example, SCITXDA could be configured to go through GPIO29 and/or GPIO35 as you mention (as well as GPIO118).  Either of these pins will work assuming that you've configured the chip correctly in software.

    (note that if you need 2 SCIs in your system, the M3's UART module can in many cases be used as a substitute for a C28x SCI module)


    Thank you,
    Brett

  • Brett,

    Thanks for the answer about how many SCI ports are available. I am assuming from the documentation that the available port is port A.  If port B does not exist why is a register set defined for port B?  Should the note I mentioned specifically say that port B does not exist on any of the M35 or M36 parts?  Or should the register set for an unimplemented peripheral be removed from the documentation?

    In addition I still need the answers to my other questions about the C28 Mode 1 setup.  Which of the two pin definitions is active in that mode?  Or are both active? I don't need 2 SCIs in my C28 core, but I do need to know which of the defined pins is the correct to wire my external circuitry to. I find it hard to believe that both sets of pins are active to the same peripheral at the same time in mode 1.

    Sincerely,

    Mike Fontes

  • Mike,

    Mentions of SCI-B in the documentation are bugs.  I will submit a bug request to have the documentation fixed.  My comment is true for both the 'M35x and 'M36x devices.

    Each GPIO pin can be independently configured to be owned by the M3 or C28x core.  Assuming that a GPIO is configured to be owned by the C28x core, it can additionally be independently configured to be in mode 0, mode 1, mode 2 or mode 3. This means that you can use the SCI at GPIO28+29 or at 35+36, etc.  This large amount of flexibility is given in order to meet differing market requirements in one device/device family.

    Hopefully this helps.


    Thank you,
    Brett