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eCAN problem with system interrupt and mailbox interrupt



Hellow,

              I am trying to use the interrupt receive the message,  I configure mailbox interrupt on Iine1,  system interrupt on line0, and I use 3 mailboxes for receive, two of them use the OPC protection(22, 21),  the key program as follows:

              

            ECanbShadow.CANMIL.all = ECanbRegs.CANMIL.all; 
            ECanbShadow.CANMIL.bit.MIL20 = 1; // configure mailbox interrupt on Iine1
            ECanbShadow.CANMIL.bit.MIL21 = 1;
            ECanbShadow.CANMIL.bit.MIL22 = 1;
            ECanbRegs.CANMIL.all= ECanbShadow.CANMIL.all ;

             ECanbShadow.CANGIM.bit.GIL = 0; // system interrupt on line0

 and I just configure ISR for mailbox 22, the program as follows:

                    

        interrupt void eCAN1INT_ISR(void)
{
        struct ECAN_REGS ECanbShadow;

       while(ECanbRegs.CANRMP.all != 0x00010000);
       ECanbShadow.CANRMP.bit.RMP22 = 1;
       ECanbRegs.CANRMP.all = ECanbShadow.CANRMP.all;
// Read data and Re–enable PIE and Core interrupts
       readH = ECanbMboxes.MBOX22.MDH.all;
       readL = ECanbMboxes.MBOX22.MDL.all;
       PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
       IER |= 0x0100;
       EINT;
       int1count++;
       return;
}

   Now the problem is coming,  I don t know how to configure the interrupt of the rest 2 mailbox on line 1 (one with OPC bit, other is not) and system interrupt on line0.

  Can some one help me,please?

      

  • Hello Xd,

    Take a look at the following post.  It may help you with the interrupts.

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/117112/417887.aspx#417887

    http://www.ti.com/lit/an/spra876a/spra876a.pdf RXMSGLST.c 

    Thanks,

  • Your "system"-Interrupt ( I guess I should read this as "some other interrupt source of CAN, such as error, timeout ect"), which you connected to CAN-INT0 will be serviced by a 2nd Interrupt service routine, provided the PIE is enabled accordingly and the vector table has a valid entry for this source. This is independent of the 2nd line.

    Regarding the mailbox-interrupts: It depends, how many mailboxes you have enabled for interrupt requests. If you enabled alll 3 for interrupts, then all 3 interrupts will trigger the same service routine. In that case you will have to make a software switch/case, based on MIV, at the beginning of this ISR. If you use the OPC feature to receive 3 complete messages of the same ID in the 3 mailboxes (20,21,,22) then you would probably use the interrupt request from the 3rd mailbox. In that case it does not make sense to enable all 3 mailboxed for interrupts. 

  • Thanks,  Bormann:

              Exactly as you said, maybe I  didn t clearly describe the question, mailbox 20, 21(with the OPC) has the same ID , and mailbox 22 (with the OPC) has another ID, the "system interrupt" means the Global Interrupt. Generally, the mailbox 20 should not be touched, but if it has a message how can I read it?  and about the MIV it isn t automatically choose the interrupt source with the high Mailbox number?

             2nd question is When I add DELAY_US(2L) in transmit side; it  get stuck (wait the TA bit set), when I delete, it s worked, but i don t know why? that is strange.

       while(1)
    {


        //DELAY_US(2L);
         ECanaShadow.CANTRS.all = 0;
         ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test
         ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

     At last, I am a newbie for eCan, if u can give me some example about interrupt for study, I would be very grateful, thanks

  • Your are still not clear.

    (1) Which MIM - bits did you set?. What would you actually like to achieve?  If you would like to get 2 messages in maiboxes 21 and 20 and request an interrupt after the 2nd message has been received, then  just enable MIM20 and use the ISR to read both mailboxes 21 and 20. If you would also get an interrupt after the first message, than set MIM21.  In the latter case, you have to use a software branch inside the ISR, because both mailboxes will trigger the same service routine. Example:

    interrupt void CAN1 (void)

    {

    unsigned int mailbox_nr;

    mailbox_nr = ECanaRegs.CANGIF1.bit.MIV1;

    if (mailbox_nr == 21) { // read mailbox 21}

    if (mailbox_nr == 20)  {// read mailbox 20}

    etc....

    If mailbox 22 is using a different ID and should also be able to request an interrupt, then set MIM22 and extent the principle from above also for mailbox22.

    (2) DELAY_US(2L);   Ths doesn't make sense at all. This function is just a software delay of 2 microseconds.  Where is the rest of your while(1) -loop?

  • Thank for your explanation,  Bormann:

           I set MIM for mail box 21 and 22, both of them with the OPC.  because mailbox 20,21 with the same ID, by the rule of mailbox priority, the message is just stored in mailbox 21, What I want is : ensure that no message is lost, so I set an additional mailbox 20 and configured to store ’overflow’ messages, I use the ISR read the message in mailbox 21, but I don t know if there is a  ’overflow’ message in mailbox 20, how can I read it? also put the read program in ISR?( same for the mailbox 22)

           (2) And that is the rest of while(1)-loop:

                I also think add a  DELAY_US(2L)  has any effect on Bit-rate, but why the 2nd board does not respond the ACK

           while(1)
     {


       //DELAY_US(2L);
         ECanaShadow.CANTRS.all = 0;
         ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test
         ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

        do
      {
         ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
      }    while(ECanaShadow.CANTA.bit.TA25 == 0 ); // Wait for TA5 bit to be set..


        ECanaShadow.CANTA.all = 0;
        ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5
        ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
        ECanaMboxes.MBOX25.MDL.all = i;
        ECanaMboxes.MBOX25.MDH.all = i+1;
        i++;
        if(i>100000)
        i=0;
        loopcount ++;
    }

  • Then also enable mbx20 for interrupts(MIM).  I f a message has been written into mbx20 (your overflow safety buffer), the interrupt will trigger the same ISR as mbx22 and 21. Use the method I explained in my last post to distinguish between the 3 differten interrupt sources.

    The delay of 2us has nothing to do with the data rate, it is totally not related to CAN. The problem in your code could be that you request the transmission directly after the previous has been just completed (busload = 100%).  Use a time delay between the transmissions.

      

  • Thanks,  Bormann:

        

           What a poor network in China, I even can t open the forum,  about the 2nd question, I still don t know how to solve, but at least I know how to figure out the 1st, and I already finished it, now I begin to program the system interrupt, I think that is the same method for the system interrupt, and I think I will have problems later with the system interrupt.