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TMS320F2835: TBCLKSYNC and the TZFLG register

Pierre Bouchet1
Expert 2615 points

Hello,

I'm testing an ISR which is triggered by a Trip Zone.

In my code I enable the peripheral clock by setting the PCLKCR1[EPWM2ENCLK] bit, then I force the interrupt, then I clear it like so:

EALLOW;
EPwm2Regs.TZFRC.bit.DCBEVT1 = 1;
EPwm2Regs.TZCLR.bit.DCBEVT1 = 1;
EPwm2Regs.TZCLR.bit.INT = 1;
EDIS;

The write to TZFRC works fine, but the writes to TZCLR won't work unless I add a line before the above snippet to start the time-base clock by setting the PCLKCR0[TBCLKSYNC] bit.

So here is my question: is this the expected behaviour?

Best Regards,

PB


  • 0
    Expert 1460 points

    Hi Pierre,

    That bit is an interrupt clear bit. So before modifying that bit disable all the interrupts. After setting that bit enable all the interrupts.

    like this:

    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    EPwm2Regs.TZCLR.bit.INT = 1;

    // Enable global Interrupts and higher priority real-time debug events:
    EINT; // Enable Global interrupt INTM
    ERTM; // Enable Global realtime interrupt DBGM

    Regard's

    Thirumoorthy.R

    If my reply answers your question please click on the green button "Verify Answer". 

  • 0 in reply to Thirumoorthy R
    Expert 2615 points

    Hi,

    Thanks for your reply. I tried it but it doesn't change anything.

    I suppose it's not a matter of clearing IER and IFR, otherwise: 1) it would work 2) why would TBCLK have - or seem to have - any influence on this?

    In the example code from TI, they clear the TZCLR[INT] from within the ISR but they never clear IER/IFR. They do, however, set TBCLKSYNC before running any interrupt code.

    Now what I'd really need is an example code that clears the interrupt flag with the Time-Base clock disabled. It would allow me to look for the problem in my code by comparing it with the example.
    Or maybe this is the expected behaviour but I missed something in the doc?
    Regards,
    P.
  • 0 in reply to Pierre Bouchet1
    TI__Guru 57255 points

    Pierre,

    Enabling the TBCLKSYNC bit is needed.

    The System Control and Interrupts Reference Guide and the ePWM User's Guide for your device should help clarify this.

    Attached is a screenshot from the 'F28035 System Control and Interrupts Reference Guide.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Expert 2615 points

    Brett,

    Thanks a lot for your answer.

    Section 4.9 in SPRUGE9E states that the ePWM registers should be initialized with TBCLKSYNC cleared, as long as the ePWM is clocked, therefore I thought I could write to TZCLR with EPWMnENCLK = 1 and TBCLKSYNC = 0. 

    Cheers,

    Pierre