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Some problems with Comparators and trip-zones

TobyM
Genius 5200 points

Hi Folks

Im having some trouble understanding how the digital-compare and trip-zone modules work together in the ePWM peripherals, seems like my head is going in circles here!

Basically I want a high output of the two comparators to cause all 3 of the PWM's I am using to set their output LOW and cause an interrupt.

The code I currently have is below. The problem Im having is understanding how I should configure TZSEL and TZEINT

If I have set the TZEL bits DCAEVT1 and DCBEVT1 does this mean they are now the OSHT source? so I should enable the OST bit in TZEINT for them to cause an interrupt? but I still use the DCAEVT1 and DCBEVT1 bits in the TZCTL register, or do I switch to TZ there?

If I do use OST in the TZEINT instead of DCAEVT1 and DCBEVT1, how can I know which comparator caused the interrupt as there will only be one flag, the OST, raised?

So confused :(

void pwmTzConfigure (void) {
   Uint16 i;
   EALLOW;
   for (i = 1; i <= 3; i++) {
      (*ePWM[i]).DCTRIPSEL.bit.DCAHCOMPSEL = 0x08;/* DC trip select COMP1 as DC A high input*/
      (*ePWM[i]).DCTRIPSEL.bit.DCBHCOMPSEL = 0x09;/* DC trip select COMP2 as DC B high input*/
      (*ePWM[i]).TZDCSEL.bit.DCAEVT1 = 0x2; /* Select DCAH=Hi & DCAL=x for DCAEVT1 */
      (*ePWM[i]).TZDCSEL.bit.DCBEVT1 = 0x2; /* Select DCBH=Hi & DCBL=x for DCBEVT1 */
      (*ePWM[i]).DCACTL.bit.EVT1SRCSEL = 0; /* DCAEVT1 is not filtered */
      (*ePWM[i]).DCBCTL.bit.EVT1SRCSEL = 0; /* DCBEVT1 is not filtered */
      (*ePWM[i]).DCACTL.bit.EVT1FRCSYNCSEL = 1; /* DCAEVT1 source is asynchronous */
      (*ePWM[i]).DCBCTL.bit.EVT1FRCSYNCSEL = 1; /* DCBEVT1 source is asynchronous */
      (*ePWM[i]).TZSEL.bit.DCAEVT1 = 1; /* Set DCAEVT1 as a OSHT trip source for this ePWM */
      (*ePWM[i]).TZSEL.bit.DCBEVT1 = 1; /* Set DCAEVT1 as a OSHT trip source for this ePWM */
      (*ePWM[i]).TZCTL.bit.DCAEVT1 = 0x2; /* Force PWM to a low state */
      (*ePWM[i]).TZCTL.bit.DCBEVT1 = 0x2; /* Force PWM to a low state */
   }


   //EPwm3Regs.TZEINT.bit.DCAEVT1 = 1; /* Enable DCAEVT1 interrupt */
   //EPwm3Regs.TZEINT.bit.DCBEVT1 = 1; /* Enable DCBEVT1 interrupt */
   //  OR
   EPwm3Regs.TZEINT.bit.OST = 1; /* Enable DCBEVT1 interrupt */

   PieVectTable.EPWM3_TZINT = &pwmTz_ISR; /* Map interrupt to ISR */
   EDIS;

   PieCtrlRegs.PIECTRL.bit.ENPIE = 1; /* Enable the PIE block */
   PieCtrlRegs.PIEIER2.bit.INTx3 = 1; /* Enable in PIE group 2 - INT 3 */
   IER |= M_INT2; /* Enable CPU INT 2 */
}

  • 0
    Genius 5200 points

    bump - anyone?

  • 0
    Genius 5200 points

    OK, so I think I finally managed to figure this out myself.

    Setting the TZSEL DCAEVT1 & DCBEVT1 bits does set them as the OSHT source, which can then be set to cause the interrupt with the TZEINT OST bit.

    However the flags for DCAEVT1 and DCBEVT1 will still be set, along with the OST and INT flags.

    To work this out I had to print out the register pages so I could reference them as I read the Trip zone description documentation, while drawing a map of how the registers "connected" to each other with event signals. I have to say, until I did that the diagrams in the documentation made no sense to me at all!!