Other Parts Discussed in Thread: TMS320F28335
Hello,
I have a question about the TMS320F28335 used in a benchmark.
It is used as a master to drive an EEPROM with the DSP-B interface.
The Clock Stop mode is used.
On the document SPRFB7A-september 2007 – Revised October 2007 on page 61,
When CLKSTOP = 10b, CLKXP=CLKRP=0, it seems that the data is transmitted on the rising edge of CLKX.
In the figure 6-37 on page 176 of TMS320F28335 Data Manual (SPRS439H-June 2007 – Revised March 2010), DX is generated on rising edge.
In our case CLKG = 8.33MHz (P=60ns). The data is generated M25-M29=60-6=54 ns before the rising edge and not on the rising edge of CLKX like in table 6-2.
Could you confirm that the DX can be generated before the CLKX rising edge in low inactive state without delay mode?