Other Parts Discussed in Thread: TMS320F28335
I use TMS320F28335 McBSP as SPI master to drive an EEPROM with the DSP-B interface.
The clock stop mode is used: CLKSTP = 10, CLKXP = 0 and CLKRP = 0.
The transmit data is output on rising edge.
The received data is sample on falling edge.
I have a question about the figure 6-37.
What is the delay between CLKX high to DX valid during an emission for all bits except the first bit transmitted with P=60ns ?