Other Parts Discussed in Thread: TMS320F28035, CONTROLSUITE
I'm having an issue with the ePWM on a TMS320F28035. I would like to generate a pure 100kHz square wave form duty cycle with no higher frequency switching. Output High duty cycle looks like a comb... _____|`|_|`|_|`|_|`|____ I want it to look like _____|``````````````|______
I've been trying to get this working for a few weeks now and have NOT been able to get this working correctly.
heres my code...
void
InitEPwm1Example()
{
EALLOW;
EPwm1Regs.
TBCTR = 300;
EPwm1Regs.
TBPRD = 300; // Set timer period 150x2=300 TBCLKs
EPwm1Regs.
TBPHS.half.TBPHS =0; // Phase is 0
EPwm1Regs.
TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Set up down count mode
EPwm1Regs.
TBCTL.bit.PHSEN = TB_DISABLE; // disable phase off set
EPwm1Regs.
TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.
TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync on timer b = 0
EPwm1Regs.
TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.
TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.
CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Setup shadowing
EPwm1Regs.
CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.
CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.
CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.
AQCTLA.bit.CAU = AQ_SET; // was AQ_CLEAR; // when compare A count up = compare value... set high
EPwm1Regs.
AQCTLA.bit.CAD = AQ_CLEAR;// was AQ_SET; // when compare A count down = compare value... set low/clear
EPwm1Regs.
AQCSFRC.bit.CSFA = 0x10; // Force Output High on PWMA.
EPwm1Regs.
AQCSFRC.bit.CSFB = 0x10; // Force Output High on PWMB.
EPwm1Regs.
DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable dead band
EPwm1Regs.
DBCTL.bit.POLSEL = DB_ACTV_HIC; // dead band active on high compare
EPwm1Regs.
DBFED = 0; // falling edge delay
EPwm1Regs.
DBRED = 0; // rising edge delay
EPwm1Regs.
PCCTL.bit.CHPEN = CHP_DISABLE; // disable PWM chopping
EPwm1Regs.
CMPA.half.CMPA = 0;// was Duty1_scale; //was 300 // Set compare A value to EPWM1_MIN_CMPA // DUTY CYCLE PERCENT CONTROL... (100= 1/3 high; 200= 2/3 high)
// EPwm1Regs.CMPB = 150; //was 150 // Set Compare B value
// Define an event (DCAEVT1) based on TZ1 and TZ2
EPwm1Regs.
DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = Comparator 1 output
EPwm1Regs.
DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2; // DCAL = TZ2
EPwm1Regs.
TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW; // DCAEVT1 = DCAH low, DCAL high;
EPwm1Regs.
DCACTL.bit.EVT1SRCSEL = DC_EVT1; // DCAEVT1 = DCAEVT1 (not filtered)
EPwm1Regs.
DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
// Enable DCAEVT1 as a one-shot trip source
// Note: DCxEVT1 events can be defined as one-shot.
// DCxEVT2 events can be defined as cycle-by-cycle.
EPwm1Regs.
TZSEL.bit.DCAEVT1 = 0; // was 1
// What do we want the one-shot trip to do?
// Because DCAEVT1 is causes a trip event
// (in this case one-shot) we need to use the TZA
// the and TZB actions to force EPWM1A and EPWM1B
// Note: TZA and TZB have higher priority over the
// DCAEVT2 action.
EPwm1Regs.
TZCTL.bit.DCAEVT1 = TZ_FORCE_LO; // EPWM1A will go high
// EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO; // EPWM1B will go low
// Enable TZ interrupt
EPwm1Regs.
TZEINT.bit.CBC = 1; // set to cycle by cycle comparator trip
EDIS;
}
When I generate a 100 percent duty cycle On output at 100kHz... I get a 100kHz square wave form with the voltage dropping from 3.3v to 0 at a rate of 1MHz and then turning back on to 3.3v.
How do I get a steady 3.3v output high on time with ePWM generation?
