GPIO Mode 15

Paul Buschmeyer

Other Parts Discussed in Thread: CONTROLSUITE

I have a sinking feeling that my version of the F28M35H52C1 YF-24AVD3W (Device ID Reg 0 = 0x20400000, Device ID Reg 1 = 0x1154804C) does not support Alternate Mode 15 Peripherial selection on Ports F, G, H, and J. We are trying to use the MII signals specified in SPRS742D (August 2012) Table 2.28. However, that document conflicts with SPRUH22B (December 2011) Table 4.1.

Below is our code to set up the pins, but we don't see any signals with the logic analyzer (e.g. no clock on MDC, etc.). We've checked the registers and they are indeed being set as intended in the code below. We are using the enet_uip_m3 example project ControlSUITE, just using different pins for the ENET interface.

Any insight will be greatly appreciated.

Thanks!

Paul

// MII_TXEN

    GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);

    GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);

    HWREG(GPIO_PORTF_BASE + GPIO_O_APSEL)|= 0x00000020;

    HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) &= 0xFF0FFFFF;

    HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) |= 0x00F00000;


// MII_TXCK, MII_TXER

    GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_0 |

    GPIO_PIN_1|

    GPIO_PIN_7, GPIO_DIR_MODE_HW);


    GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_0 |

    GPIO_PIN_1 |

    GPIO_PIN_7, GPIO_PIN_TYPE_STD);


    HWREG(GPIO_PORTG_BASE + GPIO_O_APSEL)|= 0x00000083;

    HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) &= 0x0FFFFF00;

    HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) |= 0xF00000FF;

// MII_TXD3, MII_TXD2, MII_TXD1, MII_TXD0, MII_COL, nMII_PHYRST, nMII_PHYINTR, MII_MDC

    GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_0 |

    GPIO_PIN_1 |

    GPIO_PIN_2 |

    GPIO_PIN_3 |

       GPIO_PIN_4 |

       GPIO_PIN_5 |

       GPIO_PIN_6 |

    GPIO_PIN_7, GPIO_DIR_MODE_HW);


    GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_0 |

GPIO_PIN_1 |

GPIO_PIN_2 |

GPIO_PIN_3 |

GPIO_PIN_4 |

GPIO_PIN_5 |

GPIO_PIN_6 |

GPIO_PIN_7, GPIO_PIN_TYPE_STD);


    HWREG(GPIO_PORTH_BASE + GPIO_O_APSEL)|= 0x000000FF;

    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) &= 0x00000000;

    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) |= 0xFFFFFFFF;


// MII_MDIO , MII_RXD3 , MII_RXD2 , MII_RXD1, MII_RXD0, MII_RXDV, MII_RXER, MII_RXCK

    GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_0 |

GPIO_PIN_1 |

GPIO_PIN_2 |

GPIO_PIN_3 |

GPIO_PIN_4 |

GPIO_PIN_5 |

GPIO_PIN_6 |

GPIO_PIN_7, GPIO_DIR_MODE_HW);


GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_0 |

GPIO_PIN_1 |

GPIO_PIN_2 |

GPIO_PIN_3 |

GPIO_PIN_4 |

GPIO_PIN_5 |

GPIO_PIN_6 |

GPIO_PIN_7, GPIO_PIN_TYPE_STD);


 HWREG(GPIO_PORTJ_BASE + GPIO_O_APSEL)|= 0x000000FF;

HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) &= 0x00000000;

HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) |= 0xFFFFFFFF;

over 13 years ago

0 Santosh Athuru over 12 years ago

TI__Mastermind 19810 points

Paul,

the TRM table is correct. I believe the datasheet has some pending updates.

there is no Ethernet pin functionality in alternate mode 15 on any of the PortF, PortG, Port H or Port J pins. There is some on the alternate mode 12 on the pins in these ports as shown in the TRM.

can you confirm if you are using alternate mode 12 and are seeing any issues?

Best Regards

Santosh

0 Hareesh Janakiraman over 12 years ago in reply to Santosh Athuru

TI__Guru* 95315 points

Paul,

Also, the most recent revision of the datasheet on the web is "F". Rev G should go out in about 3 weeks. That revision will have the correction Santosh is talking about.

Hareesh

0 Paul Buschmeyer over 12 years ago in reply to Santosh Athuru

Prodigy 130 points

Santosh:

No, we cannot test using the Mode 12 pins. We designed our hardware based on Rev D. of the spec sheet!!!! We will have to do a redesign and a board turn to test Mode 12 pins. WHEN IS THIS PART GOING TO BE STABLE?????? We want prototypes Q3 and pilot production Q4, can you support that?????

Paul

0 Santosh Athuru over 12 years ago in reply to Paul Buschmeyer

TI__Mastermind 19810 points

Paul,

the parts are close to TMS, so it is stable - the updated datasheet will be out soon as Hareesh pointed out above. This was a datasheet error which is already in the process of corrections.

The TRM was correct in this case and as you pointed out, there was a difference in information between datasheet and TRM which should have been hashed out.

Best Regards

Santosh

0 Paul Buschmeyer over 12 years ago in reply to Hareesh Janakiraman

Prodigy 130 points

Hareesh:

So what will change from F to G???? We have to do a redesign if the Ethernet functionality is never going to be on Mode 15 pins per SPRa742D. Is that the case? I don't want to have to throw away two designs because the plans keep changing. Which spec sheet can I rely on????? When will the silicon be available that will match spec sheet revision G????

Paul

0 Hareesh Janakiraman over 12 years ago in reply to Paul Buschmeyer

TI__Guru* 95315 points

Paul,

Rev G datasheet will be the TMS datasheet (production status). It would contain the final numbers for many electrical parameters that are not present right now. With the exception of the correction mentioned in this thread, nothing else would change on the pin muxing. The plan is to release this datasheet before the end of June.

Hareesh

0 Paul Buschmeyer over 12 years ago in reply to Hareesh Janakiraman

Prodigy 130 points

Hareesh:

OK, Thanks! That is the information I need. When will production silicon be available?

Paul

0 Hareesh Janakiraman over 12 years ago in reply to Paul Buschmeyer

TI__Guru* 95315 points

Paul,

I am told the order entry will open by end of June with shipping commencing by mid-August. If you need a handful of units before then, your ditributor/FAE may be able to help you.

Hareesh

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GPIO Mode 15