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I2C SDA latch up

Thomas Huerlimann1
Prodigy 10 points

Hi

I’m having a problem with the I2C bus using TI’s TMS320(2809). The setup uses 3x I2C slave devices (2xtemperature, 1temp/humidity) connected to the I2C which are mastered by the 2809. After some time (5-15min) the SDA line latches (to low) in the middle of the sensor communication. I have a few scope print-outs which show the moment of the latch up.  The 2809 then indicates an ‘Arbitration’-error leaving the SDA line latched to low and stops the SCL clock line immediately.

I wonder if there are any means that the 2809 can force the SDA line to go high again (apart from power cycling the device). A watchdog reset in that case did not release SDA line.

I’d appreciate any help on the issue.

kind regards

thomas

  • 0
    TI__Mastermind 20850 points

    Hi Thomas

    Thomas Huerlimann1 said:
    The 2809 then indicates an ‘Arbitration’-error leaving the SDA line latched to low and stops the SCL clock line immediately.

    First, I'm not sure why you are getting an arbitration error when you only have 1 master on the bus. According to the datasheet

    Arbitration lost. AL is set by any one of the following events:

    1. The I2C module senses that it has lost an arbitration with two or more competing transmitters that started a transmission almost simultaneously.
    2.  The I2C module attempts to start a transfer while the BB (bus busy) bit is set to 1. When AL becomes 1, the MST and STP bits of I2CMDR are cleared, and the I2C module becomes a slave-receiver.

    If its the second case, you should be polling the BB before transmitting.

    Thomas Huerlimann1 said:
    I wonder if there are any means that the 2809 can force the SDA line to go high again (apart from power cycling the device). A watchdog reset in that case did not release SDA line.

    Does resetting the I2C module(I2CMDR.IRS) help? The datasheet says you can reset in 2 ways, either using the I2CMDR.IRS or by pulling the XRS line low...which is what happens on a watchdog reset. Since you say that the WD reset doesnt help its probable that one of the slaves is driving the line low. You might have to issue a reset to all the slaves in that case, or power cycle as a last resort.

  • 0 in reply to Vishal_Coelho
    TI__Guru*** 125430 points

    In my experience with the TI I2C controller it seems that when you have back-to-back transfers there can be an issue where the controller still thinks the bus is busy (due to its own activity).  I believe this is the scenario causing the AL interrupt despite the fact there is only a single master on the bus.  What I found is that before starting the next transfer you should make sure that the MST bit has self-cleared.  I mentioned this and other items on this wiki page:

    http://processors.wiki.ti.com/index.php/I2C_Tips#Back-to-Back_Transfers

    (Sorry if this is too late to help you.  I happen to be searching for info related to an unrelated I2C issue and I stumbled across this thread and thought I'd add my two cents...)