Hi,
I have a problem with CLKXP bit.
I am using McBSP as a slave transmitter in Frame-Sync protocol. both Frame and CLK are provided by the master.
These are the settings of the peripharls.
//*************** RESET MCBSP
McbspbRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset
McbspbRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset
McbspbRegs.SPCR2.bit.XRST=0; // Transmitter reset
McbspbRegs.SPCR1.bit.RRST=0; // Receiver reset
//*************** Initialize McBSP Registers
McbspbRegs.SPCR2.all=0x0000; // XRST =0
McbspbRegs.SPCR1.all=0x0000; // RRST =0, DLB disabled
McbspbRegs.RCR2.all=0x0000; // RDATDLY = 0
McbspbRegs.RCR2.bit.RDATDLY = 0x1; // 1-bit data delay
McbspbRegs.XCR2.all=0x0000;
McbspbRegs.XCR1.all=0x0;
McbspbRegs.XCR1.bit.XWDLEN1 = 0x5; // word length = 32bit
McbspbRegs.XCR1.bit.XFRLEN1 = 0x5; // 6 word per frame
McbspbRegs.MCR2.all=0x0;
McbspbRegs.MCR1.all=0x0;
McbspbRegs.PCR.bit.CLKXM = 0x0; // external clock source from MCLKXB pin
delay_loop();
McbspbRegs.SPCR1.bit.CLKSTP = 0x0; // clk-stop mode disabled
McbspbRegs.PCR.bit.CLKXP = 0x0; // sampling on rising edge
McbspbRegs.PCR.bit.FSXM = 0x0; // FSX is created externally
McbspbRegs.PCR.bit.FSXP = 0x0; // Transmit frame-synchronization pulses are active high
McbspbRegs.SPCR2.bit.XINTM = 0x0; // IRQ when XRDY is set (DXR copied to XSR)
//************* Enable Sample rate generator
clkg_delay_loop(); // Wait at least 2 SRG clock cycles
McbspbRegs.MFFINT.bit.XINT = 1; // enable interrupts
McbspbRegs.SPCR2.bit.XRST=1; // release TX from reset
When i set CLKXP = 0, meaning transmit new data on the CLK rising edge, for some reason the data transmission is lost. you can see that there is no bitstream (green line) from the picture below.
with excactly the same code, but CLKXP = 1 (falling edge) , the bitstream is correct. (picture)
can anyone provide me an explanation of what is happening?
CLK´s first edge is a falling edge, so with CLKXP = 0, this affects the behavior of the peripherals? in other words, with CLKXP = 0, first edge of CLK MUST be a rising edge? this would sound very strange to me...
Can anyone help me with these problem? I do not have any idea of what is causing this issue, in the datasheet there is no trace of explanation.
Thanks.
