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F28069 ADC acquisition window

My question concerns Table 8-18 of SPRUH18D, and in particular the ACQPS field of the ADCSOCxCTL register. I understand why there would be a minimum acceptable acquisition window, as there must be sufficient time to establish a capacitor voltage. Hence I can see why 00h, 01h, 02h, 03h, 04h, 05h are listed as invalid selections (although it would seem more natural to specify the minimum acceptable acquisition window in terms of seconds instead of clock cycles, since different applications will use different clock frequencies). What really confuses me is that the document also includes the following excerpt:

"Other invalid selections: 10h, 11h, 12h, 13h, 14h, 1Dh, 1Eh, 1Fh, 20h, 21h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh, 37h, 38h, 39h, 3Ah, 3Bh"

Why would these be invalid selections? What is the reasoning for a periodic pattern of invalid selections?

  • Hi David,

    Your analysis as to why 0 to 5 are invalid is correct; these would not allow sufficient time for the sampling capacitor to charge even for an ideal signal source.  As for the other ACQPS values, there is a problem with the timing of the converter state machine wherin these values produce quite bad linearity and/or quite bad DC code spread.  Because this was found before we released the device, it is not an erratum, but neither has this been fixed on any subsequent silicon revision.