TMS320F28335 XINTF Problem

Scott Nortman

Other Parts Discussed in Thread: TMS320F28335

Hi,

I am trying to use the XINTF of the TMS320F28335 processor. I am successful with the 16 bit configuration as taken from the example code, _283XX_RunFromXintf.c , running on the ezDSP28335 development board.

However, I am trying to modify the example to use a 32 bit data bus. I added the following code to set the GPIO MUX registers:

...

GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; //GPIO 48 = XD 31

GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; //GPIO 49 = XD 30

GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; //GPIO 50 = XD 29

GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; //GPIO 51 = XD 28

GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; //GPIO 52 = XD 27

GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; //GPIO 53 = XD 26

GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; //GPIO 54 = XD 25

GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; //GPIO 55 = XD 24

GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; //GPIO 56 = XD 23

GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; //GPIO 57 = XD 22

GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; //GPIO 58 = XD 21

GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; //GPIO 59 = XD 20

GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; //GPIO 60 = XD 19

GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; //GPIO 61 = XD 18

GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; //GPIO 62 = XD 17

GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; //GPIO 63 = XD 16

...

And I changed the TIMING register to use the 32 bit bus

XintfRegs.XTIMING0.bit.XSIZE = 1;

...

However, I can not see any data on the upper 16 bits D[31..0].

Am I missing any steps in the above to use the 32 bits data bus?

over 12 years ago

0 Scott Nortman over 12 years ago

Prodigy 240 points

HI,

I just want to add that I am aware of the connection of the lower 16 bits of data to the external ASRAM; I have all of the data lines connected to an FPGA where I can see all of the data; the lower 16 lines are getting the data as expected, but the upper 16 is all 0...

0 Igor Gorbachev over 12 years ago

Guru 20525 points

Hello!

You can refer to functions "void InitXintf(void)" & "void InitXintf32Gpio()" from

Fullscreen 4604.DSP2833x_Xintf.c Download

//###########################################################################
//
// FILE:   DSP2833x_Xintf.c
//
// TITLE:   DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
//          Example initialization function for the external interface (XINTF).
//          This example configures the XINTF to its default state.  For an
//          example of how this function being used refer to the
//          examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################

#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File

//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF.  Doing
// so can yield unpredictable results


void InitXintf(void)
{
    // This shows how to write to the XINTF registers.  The
    // values used here are the default state after reset.
    // Different hardware will require a different configuration.

    // For an example of an XINTF configuration used with the
    // F28335 eZdsp, refer to the examples/run_from_xintf project.

    // Any changes to XINTF timing should only be made by code
    // running outside of the XINTF.

    // All Zones---------------------------------
    // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
    EALLOW;
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
    // No write buffering
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK/2
    XintfRegs.XINTCNF2.bit.CLKMODE = 1;


    // Zone 0------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING0.bit.XWRLEAD = 3;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING0.bit.XRDLEAD = 3;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING0.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING0.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING0.bit.USEREADY = 1;
    XintfRegs.XTIMING0.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING0.bit.XSIZE = 3;

    // Zone 6------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING6.bit.XWRLEAD = 3;
    XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING6.bit.XRDLEAD = 3;
    XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING6.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING6.bit.USEREADY = 1;
    XintfRegs.XTIMING6.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING6.bit.XSIZE = 3;


    // Zone 7------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING7.bit.XWRLEAD = 3;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING7.bit.XRDLEAD = 3;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

    // double all Zone read/write lead/active/trail timing
    XintfRegs.XTIMING7.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING7.bit.USEREADY = 1;
    XintfRegs.XTIMING7.bit.READYMODE = 1;  // sample asynchronous

    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING7.bit.XSIZE = 3;

    // Bank switching
    // Assume Zone 7 is slow, so add additional BCYC cycles
    // when ever switching from Zone 7 to another Zone.
    // This will help avoid bus contention.
    XintfRegs.XBANK.bit.BANK = 7;
    XintfRegs.XBANK.bit.BCYC = 7;
    EDIS;
   //Force a pipeline flush to ensure that the write to
   //the last register configured occurs before returning.

   InitXintf16Gpio();
// InitXintf32Gpio();

   asm(" RPT #7 || NOP");

}

void InitXintf32Gpio()
{
     EALLOW;
     GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3;  // XD31
     GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3;  // XD30
     GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3;  // XD29
     GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3;  // XD28
     GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3;  // XD27
     GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3;  // XD26
     GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3;  // XD25
     GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3;  // XD24
     GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3;  // XD23
     GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3;  // XD22
     GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3;  // XD21
     GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3;  // XD20
     GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3;  // XD19
     GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3;  // XD18
     GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3;  // XD17
     GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3;  // XD16

     GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3;  // XD31 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3;  // XD30 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3;  // XD29 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3;  // XD28 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3;  // XD27 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3;  // XD26 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3;  // XD25 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3;  // XD24 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3;  // XD23 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3;  // XD22 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;  // XD21 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;  // XD20 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;  // XD19 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;  // XD18 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3;  // XD17 asynchronous input
     GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3;  // XD16 asynchronous input


     InitXintf16Gpio();
}

void InitXintf16Gpio()
{
     EALLOW;
     GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;  // XD15
     GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;  // XD14
     GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;  // XD13
     GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;  // XD12
     GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;  // XD11
     GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;  // XD10
     GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;  // XD19
     GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;  // XD8
     GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;  // XD7
     GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;  // XD6
     GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;  // XD5
     GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;  // XD4
     GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;  // XD3
     GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;  // XD2
     GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;  // XD1
     GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;  // XD0

     GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;  // XA0/XWE1n
     GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;  // XA1
     GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;  // XA2
     GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;  // XA3
     GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;  // XA4
     GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;  // XA5
     GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;  // XA6
     GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;  // XA7

     GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;  // XA8
     GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;  // XA9
     GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;  // XA10
     GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;  // XA11
     GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;  // XA12
     GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;  // XA13
     GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;  // XA14
     GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;  // XA15
     GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // XA16
     GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;  // XA17
     GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3;  // XA18
     GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // XA19

     GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3;  // XREADY
	 GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3;  // XRNW
     GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;  // XWE0

     GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;  // XZCS0
     GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;  // XZCS7
     GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // XZCS6
     EDIS;
}

//===========================================================================
// No more.
//===========================================================================

and also to 4011.TI_TMS320x2833_XINTFspru949d.pdf.

Regards,

Igor

0 Scott Nortman over 12 years ago in reply to Igor Gorbachev

Prodigy 240 points

Hello Igor,

Thanks for your prompt reply; I have just reviewed the C code you suggested and checked against the code form the file. I am initalizing as shown, but I still can not get the 32 bit data bus to work...

I'll need to dig in a bit deeper...

Thank you,

Scott

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TMS320F28335 XINTF Problem