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Writing to 9 GPIOs

Matthew Krenik
Intellectual 675 points

Hello, 

I am trying to write to 9 different GPIO toggle registers that I want to keep synced in time. I figured there must be a way to link the toggle registers to a specific bit of a register in memory, so when I changed this register, everything would be changed at the same time. Unfortunately, I can't figure out how to do this on the C2000 F28069. Does this feature exist? How can I find out how to do this? Does it take any additional cycles to perform what I want to do, or just 1 write operation?

Thanks,

Matthew 

  • 0
    Guru 192875 points

    Hi Matthew,

    If you want to toggle 9 GPIOs at the same instant then; you'll have to toggle all at once:

    GpioDataRegs.GPATOGGLE.all = 1

    Else one by one toggling is possible ie for every clock cycle 1 GPIO can be toggled.

    GpioDataRegs.GPATOGGLE.bit.GPIO0 = 1

    GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1

    etc...........

    Regards,

    Gautam Iyer

  • 0 in reply to Gautam Iyer
    Guru 117855 points

    Suspect that this may be more of a, "Port Granularity" issue - friend Gautam.  ARM devices do not enforce a, "8bit/port" limit - that implementation springs from silicon vendor.

    MCUs which can accommodate/access external data and address bus - may access beyond 9 bits in sync.  This vendor's demoted M3 MCUs (certain units) had that capability.

    ARM MCUs from others - even w/out external bus capability - may access 16 bits (some - perhaps even beyond) in sync. 

    Should your device deny this capability - classic solution is to perform (wasteful - multi-port writes) to (for example) a pair of 8 bit latches.  (each latch clocked separately)  You may drive both latches from the same 8 bit port - again the individual latch clock signal must be unique - thus 2 writes are required.  This method yields up to 16 bits which - if the correct latch IC is chosen - may be presented in sync to the, "outside world." 

    Our group has achieved via use of FPGA or CPLD.

    GPIO demand can be reduced (if speed can be sacrificed) via use of Serial to Parallel ICs.  (or CPLD)  As with parallel version (above) choose a device which allows all outputs to toggle in unison.  (usually signaled by a pin labeled, "register to output clock" - this pin "banged" just post your multi-chip loads)

  • 0 in reply to cb1_mobile
    TI__Guru 60865 points

    cb1

    Port size on c28x is actually 32-bits.  I believe that if all your I/Os are contained within one port, say port A (GPIO0 to GPIO31), you should be able to perform write, clear, set, or toggle operations on any subset of the port in one 32-bit write. 

  • 0 in reply to Gautam Iyer
    Intellectual 675 points

    Gautam,

    Why can't I just say: 

    GpioDataRegs.GPATOGGLE.all = 0x 0000 01FF

    Wouldn't this toggle GPIOs 0-9? 

    Matthew

  • 0 in reply to Matthew Krenik
    TI__Guru 60865 points

    Matthew,

    Yes, that should work.

    (It would actually toggle GPIOs 0 to 8)

  • 0 in reply to Devin Cottier
    Guru 117855 points

    @Devin-

    Yours is good information - I did not know - thanks for that.  My post may have some value for those confined to 8 bits/port.  (rebrand & discarded, NRND crue...)

    Poster's question much suggested that he "bumped" against 8 bit/port limit - enforced by Stellaris.  (9 bit reference)

    Indeed should 32 bits be present/accounted for - single port - (as you state) your suggestion seems perfectly natural. 

    I'm at a loss to thus explain/justify poster's quandry...  (perhaps the motivation for his question deserves some attention...)