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Concerto - Reading GPIO configured as outputs across cores.

Wil P.
Expert 1660 points


Hello,

I have a rev B F28M35. 

I have GPIO23 set to the C28 as an output.  I can toggle it no problem from the C28 side and verify its state with a scope.

When I try to read the current value using the following macro from the M3 side:

#define uC_PWM_GEN_EN_GPIO23()      GPIOPinRead(GPIO_PORTD_BASE,GPIO_PIN_7)

It always returns 0.  Am I doing something wrong?  The errata states the following:

Advisory GPIO: Cortex™-M3/C28x Reads GPIO State as ‘0’ When the GPIO is Mapped to the
Other Core
Revision(s) Affected: 0


Details The Cortex™-M3 core reads the GPIO state as ‘0’ when the GPIO is mapped to the
C28x core. Conversely, the C28x core reads the GPIO state as ‘0’ when the GPIO is
mapped to the Cortex™-M3 core.
Workaround(s) None. This is fixed in Revision A silicon.

  • 0
    TI__Guru* 92820 points

    William,

    I really hate to even suggest this - can you double check the revision on the silicon before we debug further.  Please check it by looking at the REVID register. Address 0x883 in the C28 or address 0x400FE000 in the M3.

    Lori

  • 0 in reply to Lori Heustess
    Expert 1660 points

    There is a 1 in there.  The packaging is screen printed "YFB - ..."

    Also, these were literally hand-delivered by my local TI rep as rev B due to the issues that I had with rev 0.

    *aims toward Houston*

    If this is not Rev B I am going to <censored> in the <censored>ing <censored>, and then <censored> up the <censored> before <censored>ing <censored>. For <censored>'s sake.

    Have a nice day.

  • 0 in reply to Wil P.
    TI__Guru* 92820 points

    William Perdikakis said:
    There is a 1 in there.  The packaging is screen printed "YFB - ..."

    William,

    Thank you for  double checking for me - Yes, thankfully(!) it is Rev B. 

    Will follow-up again as soon as I check with the team. 

    -Lori

  • 0 in reply to Lori Heustess
    TI__Guru* 92820 points

    William,

    I wanted to follow-up and give you status. The holiday delayed us a bit here.  Now we are having a little trouble tracking down a Rev A/B part but are working to do so.

    -Lori

  • 0 in reply to Lori Heustess
    TI__Mastermind 19810 points

    William,

     

    to properly read the pin status of an IO on M3 while the IO is assigned to C28x core, you have to enable the GPIO on M3 by setting the proper bit for the IO in the respective GPIODEN register.

    Please let us know if you have any more questions.

     

    Best Regards

    Santosh

     

  • 0 in reply to Santosh Athuru
    Expert 1660 points

    Santosh,

    You just got yourself the honor of having my first born.  CONGRATULATIONS!!!!!1!!eleven

    That did it.

    I wondered why some of the pins worked (those that I explicitly configured as Open-Drain, in fact) while others did not.

    There are some SERIOUS PWMs going on in this lab right now.

    On a separate note: I need sleep.