We need to use the PWM outputs for 6 of the ePWMs residing on the C28 core. I am trying to set this up, and maybe I am confused, but I don’t see a way of assigning more than the outputs of ePWM1-4 to the C28. For this to happen I need to set more than the lowest 8 bits of the M3’s CSEL register for Port A. But unfortunately, writing the CSEL register depends on the bits in the CR register, and only the lowest 8 bits can be written: (page 351, Concerto F28M35x Technical Reference Manual, revised Feb 13, 2013)
Table 4-20. GPIO Commit (GPIOCR) Register Field Descriptions
Bit Field Value Description
31-8 Reserved Reserved
7-0 CR GPIO Commit
0 The corresponding GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN bits cannot be written.
1 The corresponding GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN bits can be written.
Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the NMI pin, PB7. This pin is currently the only GPIO that is protected by the GPIOCR register.
Because of this, the register type for GPIO Port B7 is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the NMI pin, PB7. To ensure that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset value
of GPIOCR for GPIO Port B is 0x0000.007F.
I have verified with the debugger that only the lowest 8 bits of the CR register are writable.
