Hi, guys
I am trying to use F28069 to do high sampling ADC. The sampling frequency should be 2 MHz (period: 500ns). I use PWM SOC to trigger the ADC DAQ. In my ADC interrupt routine, firstly I just tried to clear the flag and acknowledge the interrupt table. Here is the code I use:
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Clear ADCINT1 flag reinitialize for next SOC
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE.
I am using the CCS5.3.0 debug mode to run the project. I use to clock in code composer to check that it takes 32 clock cycles to clear the Interrupt flag and another 32 clock cycles to acknowledge the interrupt table, so in total, it takes 800ns just to clear the interrupt in the interrupt routine. I think it takes much longer time than it should be to clear the flag. I know that the debug mode of CCS may lower the actual processing rate of CPU. I was wondering whether it is the reason that causes the problem. If it is, is there anyway to get rid of this disadvantage of debug mode. If it is not, what other reason that causes the problem, and how to fix it to realize the high frequency DAQ.
Thank you for you time in advance.
Xinjun