Other Parts Discussed in Thread: TMS320F28069
We are using TMS320F28069 HRCAP2 for capturing pulse width. The system clock is 90Mhz. The HCCAP is clocked by system clock (HRCap2Regs.HCCTL.all = 0x0F;). The 995us pulse width is injected to the HRCAP2. The HCCAPCNTFALL0 register is read in falling edge interrupt and the reading is 90000 (which is 1ms). The HCCAPCNTFALL0 register have 90M x (1ms-955us) = 450 cycles more. The HRCAP2 interrupt is triggered by rising/falling edge and HCCOUNTER overflow in order to capture any pulse width longer than 65535/90M = 0.728ms. Do you have any explanation why there are 450 cycles more in the HCCAPCNTFALL0?
The following code is HRCAP2_INT and some initialization of HRCap2Regs:
HRCap2Regs.HCCTL.all = 0x0F;
HRCap2Regs.HCICLR.all = 0x1F; // clear all interrupt flags
__interrupt void TimeMonitorPulse(void)
{
EALLOW;
DINT;
if(HRCap2Regs.HCIFR.bit.RISE)
{
carry = 0;
}
else if(HRCap2Regs.HCIFR.bit.FALL)
{
onTime = ((unsigned long)HRCap2Regs.HCCAPCNTFALL0 + (unsigned long)carry*(unsigned long)UINT_MAX);
}
else if(HRCap2Regs.HCIFR.bit.COUNTEROVF)
{
carry++;
}
HRCap2Regs.HCICLR.all = 0x1F;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
EINT;
EDIS;
}
We also tried to read HCCOUNTER in rising/falling interrupt but that is not zero (the reading are over 10000). According to page 402 in the document spruh18c, "Because the HCCOUNTER starts counting at 0 after an edge is detected" Do you have any explanation why the HCCOUNTER is not reset to 0 in the rising/falling edge? (the code is not shown)
