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28069 ADC initialization issue?

Rick Gros1
Prodigy 145 points

I’m migrating a project from 28035 to 28069, and it seems that I may have discovered a possible issue with ADC initialization on the 28069. 

On the 28035: turn on ADC module clock; very next instruction writes 16 bits of data to ADCCTL1 <- this works. 

On the 28069: this sequence does not work (data is not written to ADCCTL1) … if I insert a single NOP instruction between these instructions, then it works. 

Is there some note somewhere that says we must delay before first access to the ADC module after turning on the module clock?

Thanks!

  • 0
    TI__Guru 60865 points

    Hi Rick,

    We haven't seen this before, but we will try to verify this.  I wonder if this has to do with the increased clock rate on F28069; a good experiment will be to try F28069 at 60MHz to see if it still has the issue.

  • 0 in reply to Devin Cottier
    Prodigy 145 points

    I was running both at 60MHz. Maybe something changed in implementation of the pipeline?

  • 0
    TI__Mastermind 28275 points

    Hi Rick,

    I confirmed your findings to be true for 28035 but not true for 28069. Nevertheless, this is not a bug or issue. When you enable the ADC module clock using "SysCtrlRegs.PCLKCR0.bit.ADCENCLK", there is a 2 cycle delay before it actually enables the ADC module clock. So, any write to the ADC registers during this time frame is invalid. Adding the "NOP" is one way to do it, or you could call "InitSysCtrl" at the beginning of your code to take care of all that before you enable the ADC module clock. I have included the section of the 28069 user guide that documents this, page 69. 

  • 0
    TI__Mastermind 28275 points

    Sorry Rick, looks like the attached screenshot didn't go through. I have re-included it.

    Regards,

    Frank.

  • 0 in reply to Rick Gros1
    Intellectual 485 points

    For benefit of others who might be searching, I'll note that I just got burned by this as well.  I have 28015 C code that does the following:

    SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;

    EPwm4Regs.TBPRD = 14;

    With compiler optimization enabled (-O2), the two writes occur back-to-back.  Due to the clock enable delay, the period register was not being written.  With optimization off, there is an instruction between the two writes and the PWM works as expected.

    For the 28015, the clock enable delay is documented in Section 3.1 of TMS320x280x, 2801x, 2804x DSP System Control and Interrupts (SPRU712).

    galen