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28069 Interrupt to CLA delay

Jason Rinckey
Prodigy 120 points

I'm trying to determine the delay from an interrupt source to the beginning of CLA execution to ensure I finish calculations within the same cycle. I am finding it is taking 10+ CPU clks to go from the event to CLA execution. The timing for the below takes about 21clks to go from SYNCO high to GPIO high. There are 8 instructions before the I/O is configured to go high, so where are the other 10+ CLKS? Pipeline?

This is my setup for the interrupt. I have the SYNCO pin going external for probing the start of the event.

ePWM[1]->ETSEL.bit.INTSEL = ET_CTR_ZERO; // INT on PRD event

ePWM[1]->ETSEL.bit.INTEN = 1; // Enable INT

ePWM[1]->ETPS.bit.INTPRD = ET_1ST; // Generate INT on every event

Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_EPWM1INT; //EPWM1INT; // 0=ADCINT1 1=none 2=EPWM1INT

 In the CLA code I have this at the beginning so that I can poll another pin:

_Cla1Task1:

MNOP

MNOP

;instruction to halt the CLA when debugging

.if(CLA_DEBUG = 1)

MNOP

MDEBUGSTOP

MNOP

MNOP

.endif

;task specific code

MMOVXI MR0, 0x02

MMOV16 @_EPwm2Regs.AQCSFRC, MR0

  • 0
    TI__Guru* 93800 points

    Jason Rinckey said:
    delay from an interrupt source to the beginning of CLA execution

    Jason,

    The following diagram from www.ti.com/lit/spruh18 shows an interrupt taken from the ADC but the same would apply to the PWM.  There are 3 cycles to start up the task.  Then the first instruction starts through the CLA pipeline.  The pipeline is 8 stages and the diagrm shows the progression of the first instruciton through the pipeline.  Depending on the instruction you may see the effect of it in the Exe or the W stage.

    Cheers

    Lori