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ePWM Trip-Zone Force Question

Other Parts Discussed in Thread: TMS320F28035

Hi,

I am using TMS320F28035.

If I set the trip-zone force register high, such as " EPwm1Regs.TZFRC.bit.OST = 1; ', inside a highest prioritized interrupt, how long should I expect the PWM to become low after this line of code is executed?

Thank you,

Frank

  • Hi Frank,

    Depends on the mode you use:

    Cycle-by-Cycle (CBC): Here in next pwm cycle it will get cleared/low

    One-Shot (OSHT) : Here it will not get cleared until you manually do it. 

    For more info:

    Cycle-by-Cycle (CBC):

    When a cycle-by-cycle trip event occurs, the action specified in the TZCTL register is carried out
    immediately on the EPWMxA and/or EPWMxB output. Table 19 lists the possible actions. In addition,
    the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a EPWMx_TZINT interrupt is generated if it
    is enabled in the TZEINT register and PIE peripheral.
    The specified condition on the pins is automatically cleared when the ePWM time-base counter
    reaches zero (TBCTR = 0x0000) if the trip event is no longer present. Therefore, in this mode, the trip
    event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually
    cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the
    TZFLG[CBC] bit is cleared, then it will again be immediately set.
    • One-Shot (OSHT):
    When a one-shot trip event occurs, the action specified in the TZCTL register is carried out
    immediately on the EPWMxA and/or EPWMxB output. Table 19 lists the possible actions. In addition,
    the one-shot trip event flag (TZFLG[OST]) is set and a EPWMx_TZINT interrupt is generated if it is
    enabled in the TZEINT register and PIE peripheral. The one-shot trip condition must be cleared
    manually by writing to the TZCLR[OST] bit.

    Regards,

    Gautam

  • Hi Gautam,

    Thank you for your reply.

    I'm using One-shot force.

    By  ' Carried out immediately', does it mean next clock cycle?

    Thanks,

    Frank

  • Hi Frank,

    Not next clock cycle, the moment TZn receives a low signal; the pulse would go to logic high immediately (same cycle).

    Regards,

    Gautam