Does interrupt latency include the time taken by the interrupt handler instructions?

Other Parts Discussed in Thread: TMS320F28035

Hi Lori,

I am using TMS320F28035.

This is a question related to my previous posting:

http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/280146.aspx

I checked the assembly code generated by the compiler for the trip zone ISR and found there were 3 instructions before the real task instructions.

        ASP       ; [CPU_]

       CLRC      PAGE0,OVM             ; [CPU_]

       CLRC      AMODE                 ; [CPU_]

I wonder if these 3 instructions are included in the 14 cycles interrupt latency ?

Thanks,

Frank