Writing to Concerto flash memory caused apparent lockup

Pat Harris

Other Parts Discussed in Thread: UNIFLASH, F28M36P63C2, CONTROLSUITE

When testing the ability to move code from high flash memory to low memory using ram-based flash_write, the Concerto chip appears to have hung up and will no longer operate and will not allow reprogramming. What can I do besides replace the chip?

Please respond. Thanks,

Pat

over 12 years ago

0 Igor Gorbachev over 12 years ago

Guru 20525 points

Hello!

Did you try erasing? Or communication with MCU is lost completely?

Regards,

Igor

0 Pat Harris over 12 years ago in reply to Igor Gorbachev

Genius 3890 points

Communication is lost completely. I realize now that this has happened before to at least two other boards. I tried just erasing using UniFlash, but apparently erase isn't enabled for the Concerto. In these last two cases, I was moving code from flash memory at 0x240000 to 0x220000.

Pat

0 Vivek Singh over 12 years ago

TI__Guru** 115271 points

Hi Pat,

Using memory watch window, can you tell us the values @ following address locations on Master (Cortex-M3) sub-system.

0x681000

0x200000 to 0x20000C

0x2FFFF0 to 0x2FFFFC

And values @ following address locations on Control (C28x) sub-system.

0x13FFF8 to 0x13FFFE

Regards,

Vivek Singh

0 Pat Harris over 12 years ago in reply to Vivek Singh

Genius 3890 points

Hi Vivek,

Thanks for your reply.

At address 0x00681000 the memory map displays only dashes and the note says, Error code 5, memory access not attempted by the driver.

Memory locations 0x200000 to 0x20000c : 0x20001b0c,0x00200031, 0x0021cf91, 0x0021cf9d, 0xffffffff,0xffffffff, then all 0s

Memory locations 0x2ffff0 to 0x2ffffc : (same as 0x00681000) only dashes displayed

C28x subsystem, memory locations 0x13fff8 to 0x13fffe : ffff ffff ffff ffff ffff ffff ffff ffff

FYI, I am running CCS4.2.5 on a Win7 machine. The chip is an F28M35H52C1RFPT, YFB - 34C9VCW G4. This I believe is a rev B chip. I have installed the new XML files for the UniFlash, but have not received any information as to what files should be used and where they should be loaded for CCS 4.2.5 (ref: http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/251698.aspx ). This may not have anything to do with the problem.

Thanks,

Pat

0 Pat Harris over 12 years ago in reply to Pat Harris

Genius 3890 points

Addl. information:

C28 error when attempting to download:

C28xx_0: File Loader: Data verification failed at address 0x001102A9 Please verify target memory and memory map.

Error found during data verification.

And on the CM3 side:

Cortex_M3_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

Cortex_M3_0: File Loader: Data verification failed at address 0x00200030 Please verify target memory and memory map.

Cortex_M3_0: Warning: (Error -1003 @ 0x2BC5) Internal error: Invalid parameter passed to function. Restart the application. If error persists, please report the error. (Release 5.0.429.0)

Error found during data verification.

Hope this helps.

Pat

0 Pat Harris over 12 years ago in reply to Pat Harris

Genius 3890 points

Also, error logs:

2728.ccs dl log.log

Pat

0 Pat Harris over 12 years ago in reply to Pat Harris

Genius 3890 points

Also, in examining the memory locations on the CM3, 0x200030 is the RESETISR location, but indicates all zeros. The note indictes that it is write protected. It may be that something triggered write protect on the chip. How do I remove the write protect?

Thanks,

Pat

0 Vivek Singh over 12 years ago in reply to Pat Harris

TI__Guru** 115271 points

Hi Pat,

Look like you have programmed the password locations in Flash. Not sure if that's intentional or it's getting programmed by mistake (wrong linker command file). Please refer to security section of device TRM to know how to unlock the device to enable the flash erase/program operations. I provided the addresses for F28M36x but look like you are using F28M25x device hence some of the locations are not showing actual content. Again, refer the TRM to have actual address location to get the password value programmed for other zone as well.

Regards,

Vivek Singh

0 Pat Harris over 12 years ago in reply to Vivek Singh

Genius 3890 points

Vivek,

As far as I can tell, these are the comparable memory locations for the F28M35x:

680800 - 0x68024
0xFFFFFFFF
0x00000000
0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x00000000
0x00000000
0x00000000

680480 - 0x06804a0

0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x006807C9
0x006807E9
0x006807F5
0x006804D5
0xFFFFFFFF

And the C28 side:

0x13fff8 - 0x13ffff

0xFFFF

Do these values look right to you?

How do I change them or can I change them? DO I need to replace the MCU?

Thanks,

Pat

0 Vivek Singh over 12 years ago in reply to Pat Harris

TI__Guru** 115271 points

Hi Pat,

There is dual zone security on this device for Master subsystem. Passwords for these zones are stored in flash at address "0x200000 to 0x20000C" for Zone1 and "0x27FFF0 to 0x27FFFC" for Zone2. Once these locations are programed device becomes secure and to change these values one need to erase the sectors with these address. If you are using the CCS Flash Plug-in then you need to first unlock the device by entering these address in KEYx registers and then erase the sectors. Once it's erase, device should be non-secure and that should hopefully fix the issue you are facing.

Hope this helps. Please refer the DCSM section in TRM for further details.

Regards,

Vivek Singh

0 Pat Harris over 12 years ago in reply to Vivek Singh

Genius 3890 points

Vivek,

My flash memory data for locations 0x200000 -..0c

4885.0x200000.dat

Here is my flash memory data for 0x27fff0 - f (all ffs) .

I found no DCSM section in the latest TRM for the f28m35x. Can you provide that information? Also, I do not understand how I am supposed to clear these memory locations as I cannot download any code to the device. What KEY registers are you referring to and how do I access them through CCS4.2.5?

Could you provide a step-by-step procedure for overcoming this failure to be able to write to flash?

Here is a printout of my flash control and flash error registers.

FLASH_CONTROL FRDCNTL = 0x00000F00 FBAC = 0x0000000F FBFALLBACK = 0x00000003 FBPRDY = 0x00008001 FPAC1 = 0x00000001 FPAC2 = 0x00000000 FMAC = 0x00000000 FMSTAT = 0x00000000 FRD_INTF_CTRL = 0x00000000

FLASH_ERROR ECC_ENABLE = 0x00000000 SINGLE_ERR_ADDR = 0x00000000 UNC_ERR_ADDR = 0x00200008 ERR_STATUS = 0x00000004 ERR_POS = 0x00000000 ERR_STATUS_CLR = 0x00000000 ERR_CNT = 0x00000000 ERR_THRESHOLD = 0x00000000 ERR_INTFLG = 0x00000002 ERR_INTCLR = 0x00000000 FDATAH_TEST = 0x00000000 FDATAL_TEST = 0x00000000 FADDR_TEST = 0x00000000 FECC_TEST = 0x00000000 FECC_CTRL = 0x00000000 FECC_FOUTH_TEST = 0xFFFFFFFF FECC_FOUTL_TEST = 0xFFFFFFFF FECC_STATUS = 0x00000000

Thanks,

Pat

0 Vivek Singh over 12 years ago in reply to Pat Harris

TI__Guru** 115271 points

Hi Pat,

It's a subsection inside "System Control and Interrupts" section. It's called "Code Security Module (CSM)".

To open the flash plug-in GUI in CCS, click on "Tool" -> "On-Chip Flash"

This will open a GUI. In this GUI, you'll find a section " Security Settings - Zone 1" which has 4 fields to enter PSWDx/KEx.

In this, enter the Zone 1 passwords (values from address 0x200000 -..0c) and then click on "Unlock" button and then click on "Erase Flash". This should erase the unwanted values and should un-lock the device.

Hope this works for you.

Regards,

Vivek Singh

0 Pat Harris over 12 years ago in reply to Vivek Singh

Genius 3890 points

Thanks Vivek,

Now I understand. It worked. I am now confident that I can fix my boards.

Thanks for leading me through the process.

Pat

0 Vivek Singh over 12 years ago in reply to Pat Harris

TI__Guru** 115271 points

Hi Pat,

Good to know that you are able to recover the boards, Look like these password locations are getting programmed accidently. Please ensure that you have correct linker command file so that it doesn't happens because if due to some reason passwords get programmed as 0x0 (all 128 bits) then device will lock permanently.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

Hi there,

I am also experiencing problems when programming the flash in the C28 core of the Concerto F28M36, with the chip part number F28M36P63C2. I use CCS 6.1.0.00104, under Ubuntu 14.04. However the same errors i get on CCS 6 from Win7.

I have no issues flashing code to the M3 core where everyting works smooth, only to the C28 core.

When I compile a standard linker file in a single file with the content attached below, i get compilation error for memory location of FLASH_EXE_ONLY_P0 with default location at 0x13FFF2. Attached the linker file:

Fullscreen F28M36x_Control_C28_FLASH_cmd.txt Download

/*
//###########################################################################
// FILE:    F28M36H63C2_generic_wshared_C28_FLASH.cmd
// TITLE:   Linker Command File For all F28M36x Devices
//###########################################################################
// $TI Release: F28M36x Driver Library vAlpha1 $
// $Release Date: February 27, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F28M36x_headers\cmd
// For BIOS applications add:      F28M36x_Headers_BIOS.cmd
// For nonBIOS applications add:   F28M36x_Headers_nonBIOS.cmd
========================================================= */

/* Define the memory block start/length for the F28M36x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28M36x are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block.
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   
   FLASHN      : origin = 0x100000, length = 0x002000     /* on-chip FLASH */
   FLASHM      : origin = 0x102000, length = 0x002000     /* on-chip FLASH */
   FLASHL      : origin = 0x104000, length = 0x002000     /* on-chip FLASH */
   FLASHK      : origin = 0x106000, length = 0x002000     /* on-chip FLASH */
   FLASHJ      : origin = 0x108000, length = 0x008000     /* on-chip FLASH */
   FLASHI      : origin = 0x110000, length = 0x008000     /* on-chip FLASH */
   FLASHH      : origin = 0x118000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x120000, length = 0x008000     /* on-chip FLASH */
   FLASHF      : origin = 0x128000, length = 0x008000     /* on-chip FLASH */
   FLASHE       : origin = 0x130000, length = 0x008000      /* on-chip FLASH */
   FLASHD      : origin = 0x138000, length = 0x002000      /* on-chip FLASH */
   FLASHC      : origin = 0x13A000, length = 0x002000      /* on-chip FLASH */
   FLASHA      : origin = 0x13E000, length = 0x001F80      /* on-chip FLASH */
   
   CSM_RSVD    : origin = 0x13FF80, length = 0x000070     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x13FFF0, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   FLASH_EXE_ONLY_P0  : origin = 0x13FFF2, length = 0x000002  /* Part of FLASHA.  Flash execute only locations in FLASHA */
   ECSL_PWL_P0 : origin = 0x13FFF4, length = 0x000004     /* Part of FLASHA.  ECSL password locations in FLASHA */
   CSM_PWL_P0  : origin = 0x13FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD21A, length = 0x0006A0     /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FD8BA, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE40A, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE496, length = 0x0000AA     /* IQ Math Tables in Boot ROM */

   BOOTROM     : origin = 0x3FED6A, length = 0x001200     /* Boot ROM */
   PIEMISHNDLR : origin = 0x3FFFBE, length = 0x000002      /* part of boot ROM  */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   BOOT_RSVD   : origin = 0x000002, length = 0x00009F     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x0000A1, length = 0x00035F     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */

   CTOMRAM     : origin = 0x03F800, length = 0x000380     /* C28 to M3 Message RAM */
   MTOCRAM     : origin = 0x03FC00, length = 0x000380     /* M3 to C28 Message RAM */
   
   FLASHB      : origin = 0x13C000, length = 0x002000     /* on-chip FLASH */

   DEV_EMU          : origin = 0x000880, length = 0x000180     /* device emulation registers */
   CSM              : origin = 0x000AE0, length = 0x000020     /* code security module registers */

   ADC1_RESULT      : origin = 0x000B00, length = 0x000020     /* ADC1 Results register */
   ADC2_RESULT      : origin = 0x000B40, length = 0x000020     /* ADC2 Results register */

   CPU_TIMER0       : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
   CPU_TIMER1       : origin = 0x000C08, length = 0x000008     /* CPU Timer1 registers */
   CPU_TIMER2       : origin = 0x000C10, length = 0x000008     /* CPU Timer2 registers */

   PIE_CTRL         : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
   PIE_VECT         : origin = 0x000D00, length = 0x000100     /* PIE Vector Table */
   PIE_VECT_CP      : origin = 0x000E00, length = 0x000100     /* PIE Vector Table Copy */

   DMA              : origin = 0x001000, length = 0x000200     /* DMA registers */

   ASYSCTRLCONFIG   : origin = 0x001700, length = 0x000080     /* Analog System Control Configuration Registers */

   HWBIST           : origin = 0x001780, length = 0x000040     /* HW BIST Registers    */

   FLASH_REGS       : origin = 0x004000, length = 0x000300     /* Flash Control registers */
   FLASH_ECC        : origin = 0x004300, length = 0x000040     /* Flash/OTP ECC Error Log registers */

   M3PLL            : origin = 0x004400, length = 0x000010     /* M3 PLL Clock Configuration Registers  */

   EPI_REGS            : origin = 0x004430, length = 0x000010       /* EPI Registers  */

   RAM_REGS         : origin = 0x004900, length = 0x000080     /* RAM Control registers */
   RAM_ERR_REGS     : origin = 0x004A00, length = 0x000080     /* RAM ECC/PARITY/ACCESS Error Log Registers */

   CM_MC_IPC        : origin = 0x004E00, length = 0x000040     /* C28 Control to Master IPC registers */

   MCBSPA           : origin = 0x005000, length = 0x000040     /* McBSP-A registers */

   EPWM1            : origin = 0x005100, length = 0x000080     /* EPWM1 + HRPWM registers */
   EPWM2            : origin = 0x005180, length = 0x000080     /* EPWM2 + HRPWM registers */
   EPWM3            : origin = 0x005200, length = 0x000080     /* EPWM3 + HRPWM registers */
   EPWM4            : origin = 0x005280, length = 0x000080     /* EPWM4 + HRPWM registers */
   EPWM5            : origin = 0x005300, length = 0x000080     /* EPWM5 + HRPWM registers */
   EPWM6            : origin = 0x005380, length = 0x000080     /* EPWM6 + HRPWM registers */
   EPWM7            : origin = 0x005400, length = 0x000080     /* EPWM7 + HRPWM registers */
   EPWM8            : origin = 0x005480, length = 0x000080     /* EPWM8 + HRPWM registers */
   EPWM9            : origin = 0x005500, length = 0x000080     /* EPWM9 registers (no HRPWM) */
   EPWM10           : origin = 0x005580, length = 0x000080     /* EPWM10 registers (no HRPWM) */
   EPWM11           : origin = 0x005600, length = 0x000080     /* EPWM11 registers (no HRPWM) */
   EPWM12           : origin = 0x005680, length = 0x000080     /* EPWM12 registers (no HRPWM) */

   ECAP1            : origin = 0x005A00, length = 0x000020     /* Enhanced Capture 1 registers */
   ECAP2            : origin = 0x005A20, length = 0x000020     /* Enhanced Capture 2 registers */
   ECAP3            : origin = 0x005A40, length = 0x000020     /* Enhanced Capture 3 registers */
   ECAP4            : origin = 0x005A60, length = 0x000020     /* Enhanced Capture 4 registers */
   ECAP5            : origin = 0x005A80, length = 0x000020     /* Enhanced Capture 5 registers */
   ECAP6            : origin = 0x005AA0, length = 0x000020     /* Enhanced Capture 6 registers */

   EQEP1            : origin = 0x005B00, length = 0x000040     /* Enhanced QEP 1 registers */
   EQEP2            : origin = 0x005B40, length = 0x000040     /* Enhanced QEP 2 registers */
   EQEP3            : origin = 0x005B80, length = 0x000040     /* Enhanced QEP 3 registers */

   GPIOG1REGS       : origin = 0x005F00, length = 0x0000E0     /* GPIO G1 registers */
   GPIOG1TRIP       : origin = 0x005FE0, length = 0x000020     /* GPIO trip/LPM registers */

   COMP1            : origin = 0x006400, length = 0x000020     /* Comparator + DAC 1 registers */
   COMP2            : origin = 0x006420, length = 0x000020     /* Comparator + DAC 2 registers */
   COMP3            : origin = 0x006440, length = 0x000020     /* Comparator + DAC 3 registers */
   COMP4            : origin = 0x006460, length = 0x000020     /* Comparator + DAC 4 registers */
   COMP5            : origin = 0x006480, length = 0x000020     /* Comparator + DAC 5 registers */
   COMP6            : origin = 0x0064A0, length = 0x000020     /* Comparator + DAC 6 registers */

   GPIOG2CTRL       : origin = 0x006F80, length = 0x000040     /* GPIO control registers */
   GPIOG2DAT        : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */

   SYSTEM           : origin = 0x007010, length = 0x000020     /* System control registers */

   SPIA             : origin = 0x007040, length = 0x000010     /* SPI-A registers */
   SCIA             : origin = 0x007050, length = 0x000010     /* SCI-A registers */

   NMIINTRUPT       : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */
   XINTRUPT         : origin = 0x007070, length = 0x000010     /* external interrupt registers */

   ADC1             : origin = 0x007100, length = 0x000080     /* ADC1 registers */
   ADC2             : origin = 0x007180, length = 0x000080     /* ADC2 registers */

   I2CA             : origin = 0x007900, length = 0x000040     /* I2C-A registers */

   FLASH_EXE_ONLY   : origin = 0x13FFF2, length = 0x000002     /* FLASH execution only locations */
   ECSL_PWL         : origin = 0x13FFF4, length = 0x000004     /* FLASH ECSL password locations  */
   CSM_PWL          : origin = 0x13FFF8, length = 0x000008     /* FLASH CSM password locations.  */


}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA | FLASHC      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHA | FLASHC,     PAGE = 0, ALIGN(4)
   .text               : > FLASHA | FLASHC      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0, ALIGN(4)

   flashexeonly        : > FLASH_EXE_ONLY_P0 PAGE = 0, ALIGN(4)
   ecslpasswds         : > ECSL_PWL_P0 PAGE = 0, ALIGN(4)
   csmpasswds          : > CSM_PWL_P0  PAGE = 0, ALIGN(4)
   csm_rsvd            : > CSM_RSVD    PAGE = 0, ALIGN(4)
   
   /* The following section definitions are required when using the IPC API Drivers */ 
   GROUP : > CTOMRAM, PAGE = 1 
   {
       PUTBUFFER 
       PUTWRITEIDX 
       GETREADIDX 
   }

   GROUP : > MTOCRAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }   
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML2       PAGE = 1
   .esysmem            : > RAML2       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0, ALIGN(4)
   .switch             : > FLASHA      PAGE = 0, ALIGN(4)

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA      PAGE = 0, ALIGN(4)            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML2           : > RAML2,       PAGE = 1
   DMARAML3           : > RAML3,       PAGE = 1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

   // from the other one

   /*** PIE Vect Table and Boot ROM Variables Structures ***/
  UNION run = PIE_VECT, PAGE = 1
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

/*** Peripheral Frame 0 Register Structures ***/
   DevEmuRegsFile       : > DEV_EMU,     PAGE = 1
   CsmRegsFile          : > CSM,         PAGE = 1
   UNION run =              ADC1_RESULT, PAGE = 1
   {
       AdcResultFile
       Adc1ResultFile
   }
   Adc2ResultFile        : > ADC2_RESULT,     PAGE = 1
   CpuTimer0RegsFile     : > CPU_TIMER0,      PAGE = 1
   CpuTimer1RegsFile     : > CPU_TIMER1,      PAGE = 1
   CpuTimer2RegsFile     : > CPU_TIMER2,      PAGE = 1
   PieCtrlRegsFile       : > PIE_CTRL,        PAGE = 1
   PieVectTableCopyFile  : > PIE_VECT_CP,     PAGE = 1
   DmaRegsFile           : > DMA,             PAGE = 1
   AnalogSysctrlRegsFile : > ASYSCTRLCONFIG,  PAGE = 1
   HWBistRegsFile        : > HWBIST,          PAGE = 1

/*** Peripheral Frame 1 Register Structures ***/
   FlashCtrlRegsFile : > FLASH_REGS,  PAGE = 1
   FlashEccRegsFile  : > FLASH_ECC,   PAGE = 1
   M3PllRegsFile     : > M3PLL,       PAGE = 1
   EpiRegsFile       : > EPI_REGS     PAGE = 1
   RAMRegsFile       : > RAM_REGS,    PAGE = 1
   RAMErrRegsFile    : > RAM_ERR_REGS,PAGE = 1
   CtoMIpcRegsFile   : > CM_MC_IPC,   PAGE = 1

/*** Peripheral Frame 2 Register Structures ***/
   SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
   SpiaRegsFile      : > SPIA,        PAGE = 1
   SciaRegsFile      : > SCIA,        PAGE = 1
   NmiIntruptRegsFile: > NMIINTRUPT,  PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
   UNION run =           ADC1,        PAGE = 1
   {
       AdcRegsFile
       Adc1RegsFile
   }
   Adc2RegsFile      : > ADC2,        PAGE = 1
   I2caRegsFile      : > I2CA,        PAGE = 1

/*** Peripheral Frame 3 Register Structures ***/
   McbspaRegsFile    : > MCBSPA,      PAGE = 1
   EPwm1RegsFile     : > EPWM1,       PAGE = 1
   EPwm2RegsFile     : > EPWM2,       PAGE = 1
   EPwm3RegsFile     : > EPWM3,       PAGE = 1
   EPwm4RegsFile     : > EPWM4,       PAGE = 1
   EPwm5RegsFile     : > EPWM5,       PAGE = 1
   EPwm6RegsFile     : > EPWM6,       PAGE = 1
   EPwm7RegsFile     : > EPWM7,       PAGE = 1
   EPwm8RegsFile     : > EPWM8,       PAGE = 1
   EPwm9RegsFile     : > EPWM9,       PAGE = 1
   EPwm10RegsFile    : > EPWM10,      PAGE = 1
   EPwm11RegsFile    : > EPWM11,      PAGE = 1
   EPwm12RegsFile    : > EPWM12,      PAGE = 1
   ECap1RegsFile     : > ECAP1,       PAGE = 1
   ECap2RegsFile     : > ECAP2,       PAGE = 1
   ECap3RegsFile     : > ECAP3,       PAGE = 1
   ECap4RegsFile     : > ECAP4,       PAGE = 1
   ECap5RegsFile     : > ECAP5,       PAGE = 1
   ECap6RegsFile     : > ECAP6,       PAGE = 1
   EQep1RegsFile     : > EQEP1,       PAGE = 1
   EQep2RegsFile     : > EQEP2,       PAGE = 1
   EQep3RegsFile     : > EQEP3,       PAGE = 1
   UNION run =           GPIOG1REGS,  PAGE = 1
   {
       GpioCtrlRegsFile
       GpioG1CtrlRegsFile
       GpioDataRegsFile
       GpioG1DataRegsFile
   }
   UNION run =           GPIOG1TRIP,  PAGE = 1
   {
       GpioTripRegsFile
       GpioG1TripRegsFile
   }

   Comp1RegsFile      : > COMP1,       PAGE = 1
   Comp2RegsFile      : > COMP2,       PAGE = 1
   Comp3RegsFile      : > COMP3,       PAGE = 1
   Comp4RegsFile      : > COMP4,       PAGE = 1
   Comp5RegsFile      : > COMP5,       PAGE = 1
   Comp6RegsFile      : > COMP6,       PAGE = 1
   GpioG2CtrlRegsFile : > GPIOG2CTRL,  PAGE = 1
   GpioG2DataRegsFile : > GPIOG2DAT,   PAGE = 1

/*** Code Security Module Register Structures ***/
   FlashExeOnlyFile  : > FLASH_EXE_ONLY,    PAGE = 1
   EcslPwlFile       : > ECSL_PWL,          PAGE = 1
   CsmPwlFile        : > CSM_PWL,           PAGE = 1

}

/*
*/

Below is the content of the linker file and the error:

<Linking>
"../F28M36x_Control_C28_FLASH.cmd", line 205: error: program will not fit into
   available memory.  placement with alignment/blocking fails for section
   "flashexeonly" size 0x2 page 0.  Available memory ranges:
   FLASH_EXE_ONLY_P0   size: 0x2          unused: 0x2          max hole: 0x2   
error: errors encountered during linking; "flash_programming_c28.out" not
   built

When i change the memory location of FLASH_EXE_ONLY_P0 to 0x13FF70 instead and reduce the FLASHA length to 0x001F70, i can successfuly compile the flash project, but i get the following message after i try to upload the flash.out file to the DSP flash memory:

C28xx_0: GEL Output: 
Memory Map Initialization Complete
C28xx_0: GEL Output: 
RAM Initialization Complete
C28xx_0: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

Now, this leads to something that works, but not properly. I have tested the program and it doesn't behave like the RAM version - so parts of the program must be lost when writing the Flash memory.

I don't know if it is a CCS problem, or i am doing something stupid.

FYI, i have checked the Flash passwords in the memory map of both processors and they are all the default FFFF....

So i dont know if i experience the same issues as Pat did, but i cannot get around to program the right software into the C28 processor. I had a project before, and at that time i was using CCS v.5 and at that time everything was fine. Can you please help? Should i just try to do the same thing with different versions of CCS, or it is me this time doing something stupid?

Best regards,

Ionut

0 Vivek Singh over 9 years ago in reply to Ionut Trintis

TI__Guru** 115271 points

Hi,

Before we look into this issue, can you please confirm you have installed all the latest update for this CCS? You can check for update by clicking on "Help -> Check for Updates" in CCS GUI. This will check for updates and show you list of installation which are missing. If you find something related to C2000 or emulation in this list, please install the same and re-try.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

Hi Vivek,

Thanks for your interest in helping out.
Please find attached a review of the package versions in my installation: http://s23.postimg.org/o2zx74ahn/Screenshot_from_2015_10_02_19_05_37.png

I did tried to run the "Check for update", but there seem to be an error and the update is not performed: http://s21.postimg.org/trkn8lt9j/Screenshot_from_2015_10_02_19_04_11.png

Do you think that if I upgrade to CCS 6.1.1 will help with this regard?

Best regards,

Ionut

0 Vivek Singh over 9 years ago in reply to Ionut Trintis

TI__Guru** 115271 points

Hi,

If you are not able to install the CCS updates then yes, I would recomend to re-install latest CCS.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

Hi Vivek,

I have installed the latest CCS version, and got the latest updates. I appreciate very much the improvements in the Linux GUI of the new CCS version. My brief package list can be seen here: http://s28.postimg.org/fwrynscy5/Screenshot_from_2015_10_02_20_44_30.png

When I compile with the "FLASH_EXE_ONLY_P0 : origin = 0x13FFF2, length = 0x000002", which is standard in the controlSUITE i still get the same error as before.

When i shorten the FLASHA region to fit there the "FLASH_EXE_ONLY_P0 : origin = 0x13FF70, length = 0x000002", i can compile with success as before, and using the standard target configuration i am able to flash the C28 core as well.

But it still worries me this solution, it looks like a workaround for me - what do you think?

I will actually see when I test this in the lab on the prototype that I have, to see if it behaves exactly like the RAM version.

It is positive that I can flash without strange errors or warnings like before, but I am not sure if the new memory location is ok.

Best regards,

Ionut

0 Vivek Singh over 9 years ago in reply to Ionut Trintis

TI__Guru** 115271 points

Hi,

In your cmd file look like you are aligning "FLASH_EXE_ONLY_P0" at 4 16bit boundary which is not needed.

flashexeonly : > FLASH_EXE_ONLY_P0 PAGE = 0, ALIGN(4)

Can you remove the "ALIGN(4)" from this and try it again.

Also please note that these are security settings which you are trying to program. You should not try programming these settings (address 0x13FFF2 to 0x13FFFF) if not incorporating security in your application.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

Dear Vivek,

Removing the aligning for the flashexeonly memory has solved the problem. I have tested everything and works smooth, as in the RAM version.

The fix to the original F28M26 controlSUITE linker file was:

flashexeonly        : > FLASH_EXE_ONLY_P0 PAGE = 0//, ALIGN(4)

Thank you very much for your support, keep up with the great work!

Best regards,

Ionut

0 Vivek Singh over 9 years ago in reply to Ionut Trintis

TI__Guru** 115271 points

Hi,

Good to know it's wokring fine after modifying the cmd file. Which version of F28M36x SW you have in controlSUITE. I check the version I have (v206) and I don't see this issue in cmd file. You may want to download latest controlSUITE version to avoid any such errors.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

I have used v206, and basically have taken the contents from the <F28M36x_generic_C28_FLASH.cmd> for Page 0, and Page 1 from <F28M36x_Headers_nonBIOS.cmd>. I have attached the linker file in an earlier post on this threat, so you can have a look at it.
/Ionut

0 Vivek Singh over 9 years ago in reply to Ionut Trintis

TI__Guru** 115271 points

Hi,

Following is what I see in v206 " <F28M36x_generic_C28_FLASH.cmd>" file -

    flashexeonly        : > FLASH_EXE_ONLY_P0 PAGE = 0
   ecslpasswds         : > ECSL_PWL_P0 PAGE = 0, ALIGN(4)
   csmpasswds          : > CSM_PWL_P0 PAGE = 0, ALIGN(4)
   csm_rsvd            : > CSM_RSVD    PAGE = 0, ALIGN(4)

There is no ALIGN(4) for flashexeonly here.

Regards,

Vivek Singh

0 Ionut Trintis over 9 years ago in reply to Vivek Singh

Prodigy 210 points

Hi Vivek,

You are right, this is also what I can see in my library for v206 last modified on March 5. So that should be right.
It must have been my leftover from another version, or just something that I must have inserted by mistake for some reason when developing and debugging.

Anyway, problem solved, thanks a lot for your kind support.

All the best,
Ionut Trintis

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