Concerto PBIST (self test)

Joel,

Can you post the version of ControlSuite and the TRM you are using?  We have had some updates to this and I want to ensure we are on the same revision.

Thanks,

Jason

Jason,

I have a couple of computers that I switch back and forth on, so I actually have v150 installed on the machine I'm trying to run the test on, but I did copy hw_pbist.h from a v210 machine.  Do I need something else besides that header?

The TRM that I'm looking at is Rev C from Feb 2013.

Thanks,
Joel 

Hi Joel.

Can you tell me what memories you are running PBIST on? 

Specifically, what is set in the PBIST_RINFOL and PBIST_RINFOU registers?

We cannot run PBIST on the memories that contain your program information, stack, PC etc.  So, if your program is loaded in C0-C1 memories, for example, you cannot run PBIST on C0-C1 memories..  

You could set PBIST Algo as you did to 0x1FF00001 and run the default algorithms on All ROM's and Two-port Memories.

For Single Port Memories running March13n, you would have to set both ALGO and RINFO registers to skip the memories that you have loaded your program on.  So, for the C0 and C1 memory example above, we would set ALGO = 0x00100000 (For March 13N Single Port) and RINFOU to 0x000F7800 for all Single Port memories besides C0-C1.

Hope that helps.

Patrick

Thanks,
Patrick 

Hi Patrick,

I think you have probably hit upon the source of the problem.  I guess I'm trying to test an area used by my program.  But I'm having trouble understanding the registers and how they're used.

I was just following the step by step instructions in example 2 on page 1770 of the TRM.  Line 6 says to enable memory override, which will override the values in RINFOL and RINFOU.  So, as you can see from my code above, I set the ALGO register to 0x1FF00001 and did not write to RINFOL or RINFOU since they would get overridden anyway.

That didn't work, but you mentioned in your post that I could set ALGO to 0x1FF00001 and test the ROMs and 2 port memories.  But I don't understand.  Doesn't 0x1FF00001 specify single port memories?

And you mentioned setting RINFOU to 0x000F7800 to test all single port memories besides C0 and C1, but wouldn't that also skip SHARED0 - SHARED7 and USB, which are all single port?

Maybe I'm just misunderstanding these registers.

Thanks for the help,
Joel 

Hi Joel, I had a copy/paste error above.  I just want to confirm you are executing this code on F28M35 and not F28M36, there are differences.

If you write 0x1FE00001 (Fixed typo from above) to ALGO Register with PBIST_OVER = 0x1,  it would cover all ROM memories as well as all two-port Distributed Compare memories.

In order to test all single port Distributed Compare memories (besides (C0/C1) according to table 28.1/28.2,

PBIST_ALGO = 0x00100000  (March 13N: Single Port RAM Distributed Compare)

PBIST_RINFOL = 0x00000000 

PBIST_RINFOU = 0x000F7900 (Shared 0-7, PIE0-1, C2/C3, DCAN0-5, MSG0-1, L0-3, USB)

PBIST_OVER = 0x0

So to answer your question, bit 18-19 in PBIST_RINFOU covers the shared memory and bit 8 covers USB.

Sorry for the confusion.

Thanks,
Patrick 

Hi Patrick,

I think the register settings make more sense now.  Thanks.

But I put 0x1FE00001in the ALGO register and 1 in the OVER register and I still get stuck in the while loop.  I haven't tried the single port test with 0x100000 in ALGO yet, but I'll let you know what happens.

My code is shown below.  By the way, I am using the F28M35 chip.

HWREG(SYSCTL_CRESCNF) = 0;              // Hold the C28 in reset during the test

HWREG(PBIST_PACT) = 1;                          // Enable the PBIST internal clocks
HWREG(PBIST_OVER) = 9;                         // override register
if((HWREG(NVIC_PEND2) & 0x08000000) == 0x08000000) {
    return 1;                            // Return error code 1 - PBIST interrupt already pending. Device not reset properly.
}

HWREG(PBIST_ALGO) = 0x1FE00001;                // Choose ALGO (March13N for all Single Port, Two Port Memories; Triple Read for ROM's) .
HWREG(PBIST_OVER) = 1;                                  // Memory Override. This forces the PBIST controller to override the value in the RINFOL and RINFOU registers..
HWREG(PBIST_DLR) = 0x21C;                           // Configure PBIST to run in Go/No-Go testing mode and kick off the PBIST Test

// Wait for the PBIST test to complete by polling bit 27 of the NVIC_PEND2 register
while((HWREG(NVIC_PEND2) & 0x08000000) != 0x08000000) {}

Do I need to do anything to the NVIC to enable something and make the pending flag (bit 27) show up?  

Thanks for your help,

Joel

Thank you.  That was the problem.  I had that in an earlier version of my code but forgot to put it back after messing around with it yesterday..

Patrick,

I don't know if you're still following this thread or not, but I have another problem.  

First, I turned on the override and set ALGO to test all ROMs and two port memories.  That failed, so I dug a little deeper and found that M3 boot ROM was the problem.  I ended up turning off that test (ALGO = 0x1F600001) and now it works.  That test passes every time.

However, now I'm trying to do some single port RAM tests and nothing seems to work.  I started with most of the groups selected in RINFOU, but I saw a failure every time, so I started clearing RINFOU one bit at a time.  I currently only have one bit enabled and it still fails.

This is what I currently have...

HWREG(PBIST_BASE + PBIST_ALGO) = 0x00100000; // March 13N: Single Port RAM Distributed Compare
HWREG(PBIST_BASE + PBIST_OVER) = 0;
HWREG(PBIST_BASE + PBIST_RINFOL) = 0x00000000;
HWREG(PBIST_BASE + PBIST_RINFOU) = 0x00000100; 

When I run this code I see PBIST_FSRF0 = 1, PBIST_FSRF1 = 0, PBIST_RAMT = 0x08002014, PBIST_FSRC0 = 5, and PBIST_FSRC1 = 0.

It seems like I'm only testing USB, but RGS and RDS in RAMT (0x80 and 0x00) are reporting a failure in PBIST_ROM in RINFOL.

Am I reading that correctly?

Thank you,

Joel

Joel,

Sorry if I missed it.  Which device revision are you using?

Thanks,

Jason

I have some boards with Rev 0 and some with Rev B.  I'm currently running this test on Rev B.

Joel, interesting issue.  Have you tried this on more then one RevB device?

Can you send me the contents of memory starting at address 0x400FB100-0x400FB200

I've verified your settings on my end i dont see any issues.

Thanks,

Patrick

Patrick,

I have not tried this on another Rev B device, but I will do that.

The contents of memory is kind of strange.  The memory view window shows that all those memory locations are zero.  But when I read the registers in code and save the contents to variables that I can view in the watch window, they are not zeros.  

I have attached a screenshot that shows the memory locations as well as "DebugData" in the watch window.

By the way, if I go back to the ROM test I described earlier (the one that passes), then all the memory locations in the memory window are still zeros, but the DebugData variables are different.  FSRF0 and FSRF1 are both 0, RAMT is 0x4004010, and FSRC0 and FSRC1 are both 0.

Thanks,
Joel 

Joel, can you send me your testcase?  I'll try and run it on my device to see how it works.

I've never seen the memory window blank as in your case.  Also the value of RAMT = 0x4004010 is invalid so something strange is going on.

Thanks,
Patrick 

Patrick,

I'd be happy to send whatever you need, but I'm not sure what you are referring to when you say test case.  

Sorry, can you send me your main .c code that you execute PBIST from?

Thanks,

Patrick

No problem.  Here you go.  

I've rewritten and played around with SelfTest.c many times, but right now it's written to run both the ROM test and the RAM test back to back in separate steps.  The ROM test should pass and the the RAM test should fail.

Thanks for the help

.4571.Main.C

/*
 * SelfTest.c
 *
 *  Created on: Aug 6, 2013
 *      Author: jclasquin
 */

#include "driverlib\device.h"
#include "stddef.h"
#include "hunterdef.h"

uint32 DebugData[5];

BOOL MemTestInit()
{
	BOOL bReturn = TRUE;

	HWREG(PBIST_BASE + PBIST_PACT) = 1;              // Enable the PBIST internal clocks
	HWREG(PBIST_BASE + PBIST_OVER) = 9;              // override register
	if((HWREG(NVIC_PEND2) & 0x08000000) == 0x08000000) {
	    bReturn = FALSE;                             // Error - PBIST interrupt already pending. Device not reset properly.
	}
	return bReturn;
}

BOOL StartTestAndWait()
{
	HWREG(PBIST_BASE + PBIST_DLR) = 0x21C;           // Configure PBIST to run in Go/No-Go testing mode and kick off the PBIST Test

	// Wait for the PBIST test to complete by polling bit 27 of the NVIC_PEND2 register
	while((HWREG(NVIC_PEND2) & 0x08000000) != 0x08000000) {}

	// Once complete, clear bit 27 of the NVIC_UNPEND2 register
	HWREG(NVIC_UNPEND2) = 0x08000000;

	DebugData[0] = HWREG(PBIST_BASE + PBIST_FSRF0);
	DebugData[1] = HWREG(PBIST_BASE + PBIST_FSRF1);
	DebugData[2] = HWREG(PBIST_BASE + PBIST_RAMT);
	DebugData[3] = HWREG(PBIST_BASE + PBIST_FSRC0);
	DebugData[4] = HWREG(PBIST_BASE + PBIST_FSRC1);


	if ((HWREG(PBIST_BASE + PBIST_FSRF0) != 0) || (HWREG(PBIST_BASE + PBIST_FSRF1) != 0)) {
		return TRUE;                                // Return error - Test failed
	}
	else {
	  	HWREG(PBIST_BASE + PBIST_DLR) = 0x218;       // Stop the test
	   	HWREG(PBIST_BASE + PBIST_PACT) = 0;          // Disable the PBIST controller
	   	return FALSE;                                // Return no error
	}
}


uint16 RunPBist()
{
	uint16 ulReturnValue;

	if (MemTestInit() == FALSE) {
		ulReturnValue = 2;                                 // Error 2 - Failed to init
	}
	// ROM Test - All ROM areas except M3 boot ROM.  Testing that ROM caused the test to never end (stuck in while loop waiting for NVIC_PEND2)
	else {
		HWREG(PBIST_BASE + PBIST_ALGO) = 0x1F600001;       // Choose ALGO (Two Port Memories; Triple Read for ROM's) .
		HWREG(PBIST_BASE + PBIST_OVER) = 1;                // Memory Override. This forces the PBIST controller to override the value in the RINFOL and RINFOU registers..
		ulReturnValue = (StartTestAndWait() ? 4 : 0);      // Returns 0 if pass, 4 if fail
	}
	// RAM Test
	if (ulReturnValue == 0) {
		if (MemTestInit() == FALSE)
			ulReturnValue = 2;                             // Error 3 - Failed 2nd init
		else {
			HWREG(PBIST_BASE + PBIST_ALGO)   = 0x00100000; // March 13N: Single Port RAM Distributed Compare
			HWREG(PBIST_BASE + PBIST_OVER)   = 0;
			HWREG(PBIST_BASE + PBIST_RINFOL) = 0x00000000;
			HWREG(PBIST_BASE + PBIST_RINFOU) = 0x00000100; // Shared 0-7, PIE0-1, DCAN0-5, MSG0-1, L0-3, USB, but not C0-C3 because we're using those when the M3 bootloader is running
			ulReturnValue = (StartTestAndWait() ? 5 : 0);  // Returns 0 if pass, 5 if fail
		}
	}
	return ulReturnValue;
}

By the way, I've tried commenting out the ROM test and running RAM by itself, but that produced the same result.

Wow.  That did it.  Funny how you can stare at the code for hours and not notice this stuff.

I still have 0x00002004 showing up in DebugData[2], which is RAMT but everything else is zero and the test passes.  I'm not really worried about that RAMT value, I just thought I'd let you know.

Thanks again for all the help,

Joel