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TMS320F28069 Clocking

78Sys
Expert 1540 points

Other Parts Discussed in Thread: TMS320F28069

To get CLKIN = 80MHz using Internal Oscillator 1, I have PLLCR[DIV] = 10000 and PLLSTS[DIVSEL] = 2 per Table 1-24 in the Tech. Manual to multiply the Internal Oscillator No. 1 10MHz by 16 and divide by 2 to get 80MHz.

Could I also have used PLLCR[DIV] = 01000 AND PLLSTS[DIVSEL] = 3 to achieve the 80MHz by a straight x8 multiplication,  (OSCCLK*8)/1.

What happens if I select a combination to yield CLKIN > 80MHz for the TMS320F28069 -- say, PLLCR[DIV] = 01010 and PLLSTS[DIVSEL] = 3 to yield 100MHz?

  • 0
    TI__Guru 57255 points

    78Sys,

    Both are valid and you should see very little difference between the two (10MHz*16/2 or 10MHz *8/1).  A previous member of my group mentioned at some point that having the divide-by-2 in the PLL reduces clock jitter to some extent and therefore this is what I would recommend doing by default.  I will admit that I have never personally measured the difference between these two options and therefore cannot verify his claim.

    You can theoretically do this (10MHz*10/1 = 100MHz), but you will no longer be running within the processor specifications.  We do not test at this frequency and therefore it is very possible that you will see odd behavior.  This is not recommended.  Note that the F2806x family of MCUs is rated up to 90MHz according to its datasheet.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Expert 1540 points

    The /2 to reduce jitter very interesting -- first time I heard that.

    Running over 80MHz would be for niche experimental products only -- if it fails, no harm done.

    Thanks very much.

    78Systems

  • 0 in reply to 78Sys
    Intellectual 315 points

    So what is the specified output frequency range of the PLL?  I found a note recommending that it stay above 50 MHz, but nothing in the datasheet or tech ref manual giving its maximum frequency.