DRV8301 ADC configuration

Mojo,

The InstaSPIN enabled F2806x devices are revision B. We actually need to update the Errata to designate that Rev B has the exact same Errata as Rev A.
As for the "fix", I assume you are talking abou the last line in the below errata. We chose not to implement this and instead double read and toss the first sample. It was simply easier for us to implement and works just fine at the motor control sample and conversion rates.

Details When the ADC conversions are initiated by any source of trigger in either sequential or

simultaneous sampling mode, the first sample may not be the correct conversion result.

Workaround(s) For sequential mode, discard the first sample at the beginning of every series of

conversions. For instance, if the application calls for a given series of conversions,

SOC0→SOC1→SOC2, to initiate periodically, then set up the series instead as

SOC0→SOC1→SOC2→SOC3 and only use the last three conversions, ADCRESULT1,

ADCRESULT2, ADCRESULT3, thereby discarding ADCRESULT0.

For simultaneous sample mode, discard the first sample of both the A and B channels at

the beginning of every series of conversions.

User application should validate if this workaround is acceptable in their application.

This issue is fixed completely by writing a 1 to the ADCNONOVERLAP bit in the

ADCTRL2 register, which only allows the sampling of ADC channels when the ADC is

finished with any pending conversion.

Setting the NONOVERLAP bit will cause the converter state machine to not overlap the S+H window of sample N-1 with the conversion window of sample N.  This overlap is 7 ADC clock cycles.  This can increase the amount of time needed to sample and process a series of conversions.

If each trigger causes only one conversion, then setting non-overlap mode will not affect the timings (because there is no other conversion to overlap with and save time), so go with non-overlap mode as the workaround.

If each trigger causes two conversions, then non-overlap will add 7 cycles of extra conversion time.  Compared with 13 cycles of conversion time for a discarded sample, this is a little bit better, so go with non-overlap.

If the trigger causes three conversions, it is pretty much a wash (13 cycles for discarded sample vs 14 cycles for non-overlap).  For any more than three conversions, discarding a sample will be faster.

You may also want to select non-overlap vs. discarding a sample if you are running out of SOCs, although there are creative ways to get around this. 

Thanks for the explanation, Devin. 

In our case the trigger is starting 7 conssecutive samples (8 if you count the dummy) so non-overlap and burnning a sample is preferred.

Thanks a lot for explanation Devin, I really never thought to do this calculation before...

Another question though - I saw that you're sampling the currents at A6,B6 channels, and voltage at A7,B7.

1. wouldn't it be more "accurate" to do a simultaneous sampling of 2 channels, using both sample-and-hold circuits ?

2. when using simultaneous sampling, how does the errata issue is addressed ? do we still need to drop the first sample (which is now 2 samples, as I understand) ?

thanks a lot

2. The first sample erratum will certain still apply in this case.  I believe that both samples will actually be corrupt, so you will need to throw both away (or use non-overlap).

Mojo,

In the case of motor control, with the speed of the ADC S/H it doesn't make a huge difference to do sequential sample vs. dual sample.  We have been using the sequential mode for flexibility in supporting different ADCs, but upon further discussion we will at least put in a dual sample example into the driver, if not make it the default.  This is now on the to-do list for release_10, which will be in October.