Hi communiTI!
I would like to use this thread for a question regarding the TMS320F28335 DMA pipeline specifications.
There's said that the DMA needs 4 cycles for a single read, than I suppose that the pipeline creates a delay when reading from memory or from an external interface.
With Pipeline I would think that there's a pipeline delay of 4 cycles and that (burst-) reads need 1 clockcycle, with the result delayed 4clock -cycles. Just like a pipeline-ADC. I would think that when DMA reads 16 words, that this would take 16Read + 4PipelineDelay cycles.
On a pipeline ADC the sampleresults are delayed by a pipeline because of its architecture, but it's a continuous stream equal to the ADC sys-clock rate.
Could someone please clear this up?
Best regards,
Tjarco Boerkoel