F28335 Simultaneous Sampling mode example.

This is what I wrote in my project:

void initAdc(void)
{
    AdcRegs.ADCTRL1.bit.RESET = 1;       /* Reset the ADC */
    asm(" RPT #22 || NOP");                          /* Must for ADC reset to take effect */
   
    (*ADC_cal_func_ptr)();                             /* Call the ADC_cal() function located in the Boot ROM */

/***************************************************************************************************
 * XCLKIN   SYSCLKOUT   HISPCLK   ADCTRL3[4-1]   ADCTRL1[7]   ADCCLK   ADCTRL1[11-8]   SH Width
 *                      HSPCP=3   ADCLKPS=0        CPS=0                ACQ_PS=4     5 ADC Clock
 * 30MHz     150MHz     25MHz      25MHz           25MHz      25MHz                     200ns
 *-------------------------------------------------------------------------------------------------
 *                      HSPCP=2   ADCLKPS=2        CPS=1                ACQ_PS=15
 *                     100/(2x2)  25/(2x2)       6.25/(2x1)            183.824KHz    16 ADC Clock
 * 20MHz     100MHz     25MHz     6.25MHz        3.125MHz    3.125MHz                  5.12us  
 **************************************************************************************************/
    AdcRegs.ADCREFSEL.bit.REF_SEL = 0;   
   
    AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;    /* bit7-6(11): ADCBGRFDN, reference power, 00=off, 11=on */
    AdcRegs.ADCTRL3.bit.ADCPWDN = 0x1;        /* bit5(1): ADCPWDN, main ADC power, 0=off, 1=on */
    AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x4;       /* bit4-1(0100): ADCCLKPS, clock prescaler, ADCLK=HSPCLK/[(2*ADCCLKPS)*(ADCTRL1[7] + 1)] */
    AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1;    /* bit0(1): SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling */

    DelayUs(5000);                            /* Wait 5ms before using the ADC */

    AdcRegs.ADCMAXCONV.all = 0x0007;        /* 8 double conv's (16 total) */

    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;  /* Setup conv from ADCINA0 and ADCINB0 */
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;  /* Setup conv from ADCINA1 and ADCINB1 */
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;  /* Setup conv from ADCINA2 and ADCINB2 */
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;  /* Setup conv from ADCINA3 and ADCINB3 */
    AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;  /* Setup conv from ADCINA4 and ADCINB4 */
    AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;  /* Setup conv from ADCINA5 and ADCINB5 */
    AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6;  /* Setup conv from ADCINA6 and ADCINB6 */
    AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7;  /* Setup conv from ADCINA7 and ADCINB7 */

    AdcRegs.ADCTRL1.bit.RESET = 0x0;            /* bit14(0): RESET, 0=no action, 1=reset ADC */
    AdcRegs.ADCTRL1.bit.SUSMOD = 0x00;      /* bit13-12(00): emulation suspend is ignored */
    AdcRegs.ADCTRL1.bit.ACQ_PS = 0x07;       /* bit11-8(0111): ACQ_PS (Acquisition), 0100 = 5 x ADCCLK */
    AdcRegs.ADCTRL1.bit.CPS = 0x0;                 /* bit7(0): CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2 */
    AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0;   /* bit6(0): CONT_RUN, 0=start/stop mode, 1=continuous run */
    AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0;    /* bit5(0): SEQ_OVRD, 0=disabled, 1=enabled */
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1;    /* bit4(1): SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer */

    AdcRegs.ADCTRL2.all = 0x0000;
    /* bit 15        0:      ePWM_SOCB_SEQ, 0=no action */
    /* bit 14        0:      RST_SEQ1, 0=no action */
    /* bit 13        0:      SOC_SEQ1, 0=clear any pending SOCs */
    /* bit 12        0:      reserved */
    /* bit 11        0:      INT_ENA_SEQ1, 1=enable interrupt */
    /* bit 10        0:      INT_MOD_SEQ1, 0=int on every SEQ1 conv */
    /* bit 9         0:      reserved */
    /* bit 8         0:      ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger */
    /* bit 7         0:      EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin */
    /* bit 6         0:      RST_SEQ2, 0=no action */
    /* bit 5         0:      SOC_SEQ2, no effect in cascaded mode */
    /* bit 4         0:      reserved */
    /* bit 3         0:      INT_ENA_SEQ2, 0=int disabled */
    /* bit 2         0:      INT_MOD_SEQ2, 0=int on every other SEQ2 conv */
    /* bit 1         0:      reserved */
    /* bit 0         0:      ePWM_SOCB_SEQ2, 0=no action */
}

void startAdc(void)
{

AdcRegs.ADCTRL2.all = 0x2000;

}

And the results table as below

ADCINA0 -> ADCRESULT0
ADCINB0 -> ADCRESULT1
ADCINA1 -> ADCRESULT2
ADCINB1 -> ADCRESULT3
ADCINA2 -> ADCRESULT4
ADCINB2 -> ADCRESULT5
ADCINA3 -> ADCRESULT6
ADCINB3 -> ADCRESULT7
ADCINA4 -> ADCRESULT8
ADCINB4 -> ADCRESULT9
ADCINA5 -> ADCRESULT10
ADCINB5 -> ADCRESULT11
ADCINA6 -> ADCRESULT12
ADCINB6 -> ADCRESULT13
ADCINA7 -> ADCRESULT14
ADCINB7 -> ADCRESULT15

Hope this helps

Tim

Thanks for sharing your setup, Tim. I'll work on it when I get back.