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PSFB peak current mode control

Shaik Shaik
Prodigy 30 points

Hello sir,

For my new project i am actively considering C2000 based Peak current controlled phase shift full bridge .In this regard i am referring the application note :"Implementing Phase Shifted Full Bridge DC - DC Converter with C2000 Microcontrollers",Hrishikesh Nene C2000 Systems and Applications Team,Version 1.1 – March 2012........

Question1: Refering to the Figure 12.PCMC PWM Waveforms , from the Q2 waveform,it is appearing as if the Q2,Q3 PWM is operating at a lower frequency compare to Q1,Q4 PWM especially when load peak current refernce is increased. It seems that when the peak current reference is increased Q2 turn on time increases beyond the Switching period/2. Suggesting a variable frequency operation for Q2,Q3 PWM is this my understanding is correct?

Question2: Figure 11.PCMC Block Diagram , the Ipri signal is derived from the ADC block which is shown as 100KHz.  For peak current control the comparator has to actively trip the PWM switches for both positive half and the negative half cycle of the current waveform, which requires a sampling of 200kHz. However the diagram implies that the comparator is actively controlling the PWM only in one half cycle of the PWM period. Is my understanding correct ?

Regards

Meeravali

  • 0
    TI__Genius 10820 points

    Hi Meeravali,

    1. This is not variable frequency operation. A large increase in the control command is used for depiction purposes only. In reality the amount of control command increase will be decided by the control law and it won't be this drastic (in most cases). The figure is merely trying to show the effect of increasing control command, which shows up as a change in phase shift of PWM signals driving switches in one leg of the full bridge with respect to PWM signals driving switches in the other leg of the switch (same frequency).

    2. The depiction in figure 11 is wrong. In the actual implementation the feedback current is directly fed to the on-chip analog comparator input. This figure needs to be corrected as shown in the attachment.

    I hope this helps.0572.Corrected_Figure_11.pdf

    - Hrishi

  • 0 in reply to Hrishi Nene
    Prodigy 30 points

    Hello Hrishi,

    Thanks for  the reply. I understand that the Q1,Q4 are free running with 50% duty cycle. In the figure12: the Q3 is also running with 50% duty cycle and the Q2 is controlled based on the peak current reference, is my understanding is correct ?

    Regards,

    Meeravali shaik