Other Parts Discussed in Thread: TEST2
I have write code like below attached but I am not getting any output on CAN bus.
#include "DSP2803x_Device.h"
#include "DSP28x_Project.h"
#include "DSP2803x_cpuTimers.h"
void delay(unsigned char );
void Gpio_select();
void InitECana(void) ;
void Can_tx(unsigned char BIDE ,unsigned int BID,unsigned char BDLC ,unsigned long Data1,unsigned long Data2);
void Can_rx(void);
void InitAdc(void);
void ADC_Conv(void);
__interrupt void cpu_timer0_isr(void);
unsigned long Data1;
unsigned long Data2;
unsigned int Bdata;
extern unsigned char i;
unsigned int num_of_bytes = 512;
Uint32 TestMbox1 = 0;
Uint32 TestMbox2 = 0;
Uint32 TestMbox3 = 0;
void main(void) {
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2803x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2803x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2803x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
InitPieVectTable();
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
Gpio_select();
InitECana();
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, 60, 100);
// InitI2Ca();
InitAdc();
delay(2);
EDIS;
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2803x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
CpuTimer0Regs.TCR.all = 0x4000; // Use write-only instruction to set TSS bit = 0
IER |= M_INT1;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
while(1)
{
//GpioDataRegs.GPADAT.all= 0x00000820;
ADC_Conv();
delay(10);
GpioDataRegs.GPASET.bit.GPIO5=1;
GpioDataRegs.GPACLEAR.bit.GPIO11=1;
delay(10);
GpioDataRegs.GPACLEAR.bit.GPIO11=0;
GpioDataRegs.GPACLEAR.bit.GPIO5=0;
delay(10);
Can_rx();
delay(5);
Can_tx(0,0x0004,8 ,Data1,0x89ABCDEF);
//EEPROM_Read(I2cMsgOut1);
GpioDataRegs.GPACLEAR.bit.GPIO5=1;
GpioDataRegs.GPASET.bit.GPIO11=1;
delay(10);
GpioDataRegs.GPACLEAR.bit.GPIO11=0;
GpioDataRegs.GPACLEAR.bit.GPIO5=0;
delay(10);
}
}
void Gpio_select()
{
// GpioCtrlRegs.GPAMUX1.all = 0X00000000;
// GpioCtrlRegs.GPADIR.all= 0x00000820;
/*LEDS*/
// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO11
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0; // GPIO11 = GPIO11
// GpioDataRegs.GPASET.bit.GPIO5 = 1; // Load output latch
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1; // GPIO11 = output
// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11
// GpioDataRegs.GPASET.bit.GPIO11 = 1; // Load output latch
GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output
/*ECAN*/
// Enable internal pull-up for the selected CAN pins
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
// Set qualification for selected CAN pins to asynch only
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
// Configure eCAN-A pins using GPIO regs
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
/* ADC */
GpioCtrlRegs.AIOMUX1.bit.rsvd6 = 1; // Configure rscd6 for B0 (analog input) operation
GpioCtrlRegs.AIOMUX1.bit.rsvd8 = 1; // Configure rsvd8 for B3 (analog input) operation
GpioCtrlRegs.AIODIR.bit.rsvd6 = 0; //Direction Configure for B0 (analog input) operation
GpioCtrlRegs.AIODIR.bit.rsvd8 = 0;
/*I2C*/
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
/* Configure I2C pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be I2C functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
}
void Can_tx(unsigned char BIDE ,unsigned int BID,unsigned char BDLC ,unsigned long Data1,unsigned long Data2)
{
ECanaRegs.CANTRS.bit.TRS0=0;
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
ECanaMboxes.MBOX0.MSGID.bit.AME=0;
ECanaMboxes.MBOX0.MSGID.bit.AAM=0;
ECanaMboxes.MBOX0.MSGID.bit.IDE = BIDE;
ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = BID;
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANMD.bit.MD0 = 0; //1 receive and 0 TXT, remaining not used
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANME.bit.ME0 = 1;
ECanaMboxes.MBOX0.MSGCTRL.all = 0;
ECanaMboxes.MBOX0.MSGCTRL.bit.DLC =BDLC;
ECanaMboxes.MBOX0.MSGCTRL.bit.RTR =0;
ECanaMboxes.MBOX0.MDL.all = Data1;
ECanaMboxes.MBOX0.MDH.all = Data2;
delay(1);
ECanaRegs.CANTRS.bit.TRS0=1;
delay(1);
// while(ECanaRegs.CANTA.bit.TA0 != 0)
// {
// ECanaRegs.CANTA.bit.TA0 =0;
// }
}
void Can_rx()
{
volatile struct MBOX *Mailbox;
ECanaRegs.CANME.bit.ME1 = 0; // Required before writing the MSGIDs
ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x0008;
ECanaMboxes.MBOX1.MSGID.bit.AME = 1;
ECanaLAMRegs.LAM1.all = 0X8008;
ECanaRegs.CANMD.bit.MD1 = 1; //1 receive and 0 TXT, remaining not used
ECanaRegs.CANME.bit.ME1 = 1;
if(ECanaRegs.CANRMP.bit.RMP1 == 1)
{
Mailbox = &ECanaMboxes.MBOX1;
TestMbox1 = Mailbox->MDL.all; // = 0x9555AAAn (n is the MBX number)
TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant)
TestMbox3 = Mailbox->MSGID.all;// = 0x9555AAAn (n is the MBX number)
}
ECanaRegs.CANRMP.bit.RMP1 = 0;
}
void InitECana(void) // Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. */
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
/* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
See Note at end of file. */
// ECanaShadow.CANBTC.bit.BRPREG = 8;
// ECanaShadow.CANBTC.bit.TSEG2REG = 2;
// ECanaShadow.CANBTC.bit.TSEG1REG = 10;
ECanaShadow.CANBTC.bit.BRPREG = 7;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
//
// ECanaShadow.CANBTC.bit.SJWREG=1;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
}
__interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; // Clear ADCINT2 flag reinitialize for next SOC
PieCtrlRegs.PIEACK.all = 0xFFFF;
}
void InitAdc(void)
{
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power ADC BG
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 1; // Select interal BG
}
void ADC_Conv()
{
unsigned int Test1,Test2;
//Test4,Test5,Test6;
unsigned long Test3;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 0;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enable ADCINT2
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 8; // setup EOC1 to trigger ADCINT2 to fire
AdcRegs.ADCSOC8CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC8CTL.bit.TRIGSEL = 1; // set SOC1 start trigger on EPWM1A
AdcRegs.ADCSOC8CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enable ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 1; // Disable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2SEL = 11; // setup EOC1 to trigger ADCINT2 to fire
AdcRegs.ADCSOC11CTL.bit.CHSEL = 11; // set SOC1 channel select to ADCINB3
AdcRegs.ADCSOC11CTL.bit.TRIGSEL = 1; // set SOC1 start trigger on EPWM1A
AdcRegs.ADCSOC11CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
// Setup each SOC's ADCINT trigger source
AdcRegs.ADCINTSOCSEL2.bit.SOC8 = 2; //ADCINT2 starts SOC0-7
AdcRegs.ADCINTSOCSEL2.bit.SOC11 = 2;
delay(1);
//Wait for ADCINT1 to trigger, then add ADCRESULT0-7 registers to sum
// while (AdcRegs.ADCINTFLG.bit.ADCINT2 != 1){}
AdcRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //Must clear ADCINT1 flag since INT1CONT = 0
Test1= AdcResult.ADCRESULT8;
Test2= AdcResult.ADCRESULT11;
Test3=( Test2 << 15 || Test1 );
delay(1);
Can_tx(0,0x0008,8 ,Test3,0X12345678);
delay(1);
}
void delay(unsigned char i)
{
long int k,j;
for(k=0;k<=i; k++)
{
//90ms time
for(j=0;j<64000;j++);
}
}
Regards,
chowdaiah
