Hello
Processor is delfino 28346.
We have a problem with spurious interrupts in group 1 when we use the S/W Priority handling as in the examples of Ti.
Following interrupts are enabled in group 1:
#define G11PL 0 // reserved
#define G12PL 0 // reserved
#define G13PL 0 // reserved
#define G14PL 3 // XINT1 (FPGA Interrupt)
#define G15PL 3 // XINT2 (ARM Interrupt)
#define G16PL 0 // reserved
#define G17PL 1 // TINT0 (CPU Timer 0)
#define G18PL 5 // WAKEINT (WD/LPM)
In our test, TINT0 is active and interrupt is triggered every 125us. On XINT1, no interrupts are triggered, on XINT2 about every 330us an asynchronous interrupt is triggered.
This works well for 1-5 hours, and then suddenly interrupt 1.1 is triggered, though it is never activated. The NOTUSED interrupt handler is called and system is stopped. I have checked the state of PIEIER1, interrupt 1.1 is not enabled, though it is called! I have read in the PIE manual, that if no interrupt is enabled in a group and the group interrupt is called, then the highest H/W priority interrupt is called. That seems to happen here. But I don't understand the reason, as we use the S/W priority handling as in the TI examples.
When I remove the priority handling stuff from the TINT0 interrupt handler (which has the highest S/W priority), then the false interrupts don't happen anymore.
See below the working and the not working version of the TINT0 handler.
Does anybody have an explanation for this behaviour?
Regards,
Daniel
Not working:
interrupt void cpu_timer0_isr (void)
{
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= M_INT1; // Set "global" priority
IER &= MINT1;
PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
EINT;
hw_amp_do_loop(((CpuTimer0.InterruptCount % PWM_RELOAD) == 0));
// Restore registers saved:
DINT;
PieCtrlRegs.PIEIER1.all = TempPIEIER;
}
Working:
interrupt void cpu_timer0_isr (void)
{
hw_amp_do_loop(((CpuTimer0.InterruptCount % PWM_RELOAD) == 0));
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
