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F28335 ADC

Dan LaChance
Expert 1770 points

Hello TI,

From my customer - please see below:

===============================================

We had some problem with ADC sampling using DSP F28335. Voltage waveform were clipping over a certain voltage level for some ADC channel. After increase the acquisition time from 40nsec to 80nsec, the problem appear to be fixed. The sampling frequency for each channel is 10KHz.

 

My basic understanding is that the internal circuit of the ADC needs time to settle during sampling. The two sample and hold of the internal ADC for F28335 are multiplexed and support max 16 channels. The circuit model of the internal ADC has input ESD capacitor, the sampling switch SW with an equivalent on-resistance RSW to the sampling capacitor CSH. When we apply a step voltage input to the circuit, min acquisition time will allow the voltage across CSH to stabilize to 1/2 of LSB.

 

I was able to follow the app note below to calculate the min acquisition time for ADC.

http://www.ti.com/lit/an/sbaa173a/sbaa173a.pdf

 

I was able to reproduce the same answer as shown as example in the app note, using the circuit values given. 

 

For our design, we drive each ADC channel using op-amp followed by an analog switch. R1 is our analog switch resistance which is max 100 Ohm. C1 is the input capacitor specified by the data sheet of F28335 as typical 10nF. 

 

In the app note, C2 (CSH) is 50pF, R2 (RSW) was given in 20 Ohm or 2000 Ohm in the example.

 

If I use R2=20 Ohm and C2=50pF, the min t_ACQ is 80.9 nsec. 

If I use R2=100 Ohm and C2=50pF , the min t_ACQ is 124.5 nsec.

 

I would like to confirm if I can follow the app note above to calculate the min acquisition time for the ADC of F28335 for our design. If yes, what would be the CSH (sample and hole capacitor) and RSW (switch resistance) for the ADC of F28335 that I can use for calculation?

 

If this is not the proper app note to follow, do you have any other reference document that can be used to determine the min acquisition time for the ADC of F28335?

  • 0
    TI__Guru 60865 points

    Dan,

    I think you are on exactly the right path.  The F28335 input model is in the datasheet (reproduced below).

  • 0 in reply to Devin Cottier
    Expert 1770 points

    Hi Devin,

    If I use the circuit parameters (RSW=1kOhm, CSH=1.64pF), then the calculated min acquisition time is only 25nsec. We are seeing problem even with 40nsec. So can I still follow the app note sbaa173a to calculate the acquisition time for F28335 ADC? or there is something else to consider?

     I wonder if there are other things which are not set properly in the ADC driver software. Can we run the ADC clock at 25MHz?

    Thanks,

    Dan

  • 0 in reply to Dan LaChance
    TI__Guru 60865 points

    Dan,

    I think the app note is correct.  The problem is probably somewhere else in the ADC setup.  

    You can definitely run the ADC at 25MHz.  It is worth carefully checking the clock divider settings to determine if that is what you are actually getting.

    Can you post your ADC initialization code?  

    Can you clarify the clipping issue that you are seeing?  At what voltage does the input clip?

    To further verify that the issue is not in the acquisition window, you could use the working sample window setting, and then start adding additional series resistance to the ADC input.  As you increase the resistance, you can see if you eventually get clipping again, or some other issues.  In my experience, if you have inadequate sampling window, the error you see will be something more like signal attenuation or cross-talk from another signal that you are sampling, not clipping.  

  • 0 in reply to Devin Cottier
    TI__Genius 16811 points

    Dan, if you happen to be running in simultaneous sampling mode (AdcRegs.ADCTRL3.bit.SMODE_SEL = 1) please be advised of a device erratum (ADC: Simultaneous Sampling Latency) that could be affecting you.  Per Devin's request, the ADC init code would be helpful to rule this out.

    Regards, Joe