[Concerto] C28 Boot Problem (not because of IPCMtoC...)

Disona,

There are few things to be careful of here, when running the dual core subsystem with emulator connected (NOT STANDALONE).

The function IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH) on M3 application is sending a boot mode IPC command to C-Boot ROM. Now with emulator connected you need to make sure the C-Boot ROM (C28x core) is running before the M3 application sends the IPC command.

Now after you connect CCS to both the cores, what users usually do is load code on both the cores and run them. At the end of load the program control is at the entry point of the application not in boot ROM. Users then run both the core which will directly run the application. But in a stand-alone mode (no debugger or CCS connected) when the M3 application is running C28x is still running its boot ROM waiting for IPC command.

you can do one of the below to help you debug.

comment out the IPCMtoCBootControlSystem function all when running M3 and C28x with debugger connected. Since you load code to C28x flash/RAM using CCS the program control is already out of boot ROM here.

or (if you don't want to comment anything)

1.> connect both the cores, debug reset and load application in flash or RAM

2.> debug reset both the cores (assuming you have GEL scripts, they would initialize the system)

3.> run M3 application, put a break point before the IPCMtoCBoot function or halt at main()

4.> debug reset C28x and run (now C28x is running boot ROM)

5.> now run M3 applicaton, C28x would also run its application in C-Flash.

Hope it helps, please let us know if you have any further questions.

Best Regards

Santosh

Hello, Santosh.

Thank you, for your help, but it didn't help, unfortunately. I'm always doing it that way. Problem is, that sometimes it works, and sometimes not. For example, i've repeated that 5 steps 25 times. 5 times were succesful, other 20 were not.

Just in case: C28 uses ePWM, GPIO and ADC. M3 uses CAN and a timer. Both cores use Shared RAM (S0 for M3 and S1 for C28).

By the way, I'm sure, there must be a special function for M3, that initialises Shared RAM (needed for standalone mode), but I didn't found it in Concerto Workshop PDFs =( So I use the command "HWREG(RAM_CONFIG_BASE + RAM_O_MSXRTESTINIT1) = 0x5; // Init" is that right?

 

Disona,

the problem is definitely because C28x core is trying to access some shared resources or those resources that are owned by M3 by default on reset. So you will have to make sure that the master has assigned/initialized the resources properly before C28x accesses it on every debug run. Try to add synchronizations between M3and C28x using IPC, like C28x waits for certain IPC flash to be set, and M3 sets that flag after the initialization is done. For shared memories C28x can do a simple read/write test to know if the ownership has been assigned properly or not.

The Shared RAM config register can be found in TRM, look for MSxMSEL in the Internal memories chapter.

hope it helps.

Best Regards

Santosh