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Fail to detect watchdog timeout via WDFLAG

Tom Bomadil
Prodigy 100 points

Other Parts Discussed in Thread: TMS320F2808

My target is the TMS320F2808 which has a WDFLAG bit in the WDCR register that is (according to my interpretation of the System Control and Interrupts Reference Guide) a neat way to check at start up if there's been a watchdog timeout. 

I put an infinite loop into my code such that at the 5-sec mark, the watchdog times out. I also put some code into Main.c that checks the WDFLAG bit and alerts me if it's been set. Thereafter, I clear the WDFLAG by writing a zero to it. Every 5 sec., my program resets, but I am never alerted that WDFLAG is set.

Should this basic strategy be expected to work?

  • 0
    Prodigy 100 points

    To clear the WDFLAG, I write a one to it (I meant).

  • 0
    Guru 13185 points

    Hello Peter,

    I think checking WDFLAG is fine if you set your WD as WDRST.

    Just to make sure:

    Did you set WDRST for your WD?
    In SCSR:
    WDENINT = 0 //for WDRST
    WDENINT = 1 //for WDINT

    Then in the app document,
    'If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to
    the WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDFLAG) in the WDCR register.
    After a reset, the program can read the state of this flag to determine the source of the reset.'


    So when WDCR overflow, WDFLAG becomes 0 (get set).


    How did you check this WDFLAG?
    Can you get the value of WDFLAG whether it is 0 or 1 after reset?

    Did you reset your watchdog counter after reset (I assume you did because you said that your program resets every 5s).


    From the F2808 datasheet, I got:
    'During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles.'

    And from app document,

    'When the XRS line is low, the WDFLAG bit is forced low. The WDFLAG bit is only set if a rising edge on WDRST signal is detected (after synch and an 8192 SYSCLKOUT cycle delay) and the XRS signal is
    high. If the XRS signal is low when WDRST goes high, then the WDFLAG bit remains at 0. In a typical
    application, the WDRST signal connects to the XRS input. Hence to distinguish between a watchdog reset
    and an external device reset, an external reset must be longer in duration then the watchdog pulse.'

    Maybe you should check your XRS signal too.

    Good luck!

    Best regards,
    Maria,